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Commit 2bfac3a5 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'socfpga-dt-updates-for-3.16_v3' of... 

Merge tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next into next/dt

Merge "dts: socfpga: general updates for the socfpga platform" from Dinh
Nguyen:

Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a
couple of device tree documentation updates/typo fix.

This one does not the GPIO binding patch, as that is pending further
discussion. Also, v3 fixes a rebase artifact and compile tested.

* tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next

:
  ARM: socfpga: dts: Add div-reg to the main_pll clocks
  ARM: socfpga: dts: add reset-controller
  Documentation: dt: reset: move socfpga-reset
  Documentation: dt: socfpga: add reset-cells property
  ARM: socfpga: dts: Add DTS entries for USB
  ARM: socfpga: dts: Remove hard coded clock-frequency property
  ARM: socfpga: dts: add eeprom and rtc on i2c0
  ARM: socfpga: dts: convert to preprocessor includes
  ARM: socfpga: dts: add rtc on i2c0 to socrates
  ARM: socfpga: dts: add support for EBV SOCrates
  ARM: socfpga: dts: add can0+1
  ARM: socfpga: dts: add i2c busses
  ARM: socfpga: dts: add remaining interrupts for pdma
  ARM: socfpga: dts: fix pdma interrupt

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2542f928 8cb289ed

Documentation/devicetree/bindings/clock/altr_socfpga.txt

+2 −2
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@ Optional properties: 
- fixed-divider : If clocks have a fixed divider value, use this property.

- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register

        and the bit index.

- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,

        and width.

- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains

	the divider register, bit shift, and width.

- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls

	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second

	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt→Documentation/devicetree/bindings/reset/socfpga-reset.txt

+2 −0
Original line number Diff line number Diff line
@@ -3,9 +3,11 @@ Altera SOCFPGA Reset Manager 
Required properties:

- compatible : "altr,rst-mgr"

- reg : Should contain 1 register ranges(address and length)

- #reset-cells: 1



Example:

	 rstmgr@ffd05000 {

		#reset-cells = <1>;

		compatible = "altr,rst-mgr";

		reg = <0xffd05000 0x1000>;

	};

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \

	socfpga_cyclone5_socdk.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_cyclone5_socrates.dtb \

	socfpga_vt.dtb

dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \

	spear1340-evb.dtb

arch/arm/boot/dts/socfpga.dtsi

+112 −6
Original line number Diff line number Diff line
@@ -15,7 +15,8 @@ 
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



/include/ "skeleton.dtsi"

#include "skeleton.dtsi"

#include <dt-bindings/reset/altr,rst-mgr.h>



/ {

	#address-cells = <1>;
@@ -75,7 +76,14 @@ 
			pdma: pdma@ffe01000 {

				compatible = "arm,pl330", "arm,primecell";

				reg = <0xffe01000 0x1000>;

				interrupts = <0 180 4>;

				interrupts = <0 104 4>,

					     <0 105 4>,

					     <0 106 4>,

					     <0 107 4>,

					     <0 108 4>,

					     <0 109 4>,

					     <0 110 4>,

					     <0 111 4>;

				#dma-cells = <1>;

				#dma-channels = <8>;

				#dma-requests = <32>;
@@ -84,6 +92,22 @@ 
			};

		};



		can0: can@ffc00000 {

			compatible = "bosch,d_can";

			reg = <0xffc00000 0x1000>;

			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;

			clocks = <&can0_clk>;

			status = "disabled";

		};



		can1: can@ffc01000 {

			compatible = "bosch,d_can";

			reg = <0xffc01000 0x1000>;

			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;

			clocks = <&can1_clk>;

			status = "disabled";

		};



		clkmgr@ffd04000 {

				compatible = "altr,clk-mgr";

				reg = <0xffd04000 0x1000>;
@@ -124,7 +148,7 @@ 
							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <2>;

							div-reg = <0xe0 0 9>;

							reg = <0x48>;

						};
@@ -132,7 +156,7 @@ 
							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <4>;

							div-reg = <0xe4 0 9>;

							reg = <0x4C>;

						};
@@ -140,7 +164,7 @@ 
							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <4>;

							div-reg = <0xe8 0 9>;

							reg = <0x50>;

						};
@@ -460,6 +484,8 @@ 
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */

			clocks = <&emac0_clk>;

			clock-names = "stmmaceth";

			resets = <&rst EMAC0_RESET>;

			reset-names = "stmmaceth";

			status = "disabled";

		};
@@ -472,6 +498,48 @@ 
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */

			clocks = <&emac1_clk>;

			clock-names = "stmmaceth";

			resets = <&rst EMAC1_RESET>;

			reset-names = "stmmaceth";

			status = "disabled";

		};



		i2c0: i2c@ffc04000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0xffc04000 0x1000>;

			clocks = <&l4_sp_clk>;

			interrupts = <0 158 0x4>;

			status = "disabled";

		};



		i2c1: i2c@ffc05000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0xffc05000 0x1000>;

			clocks = <&l4_sp_clk>;

			interrupts = <0 159 0x4>;

			status = "disabled";

		};



		i2c2: i2c@ffc06000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0xffc06000 0x1000>;

			clocks = <&l4_sp_clk>;

			interrupts = <0 160 0x4>;

			status = "disabled";

		};



		i2c3: i2c@ffc07000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0xffc07000 0x1000>;

			clocks = <&l4_sp_clk>;

			interrupts = <0 161 0x4>;

			status = "disabled";

		};
@@ -508,24 +576,32 @@ 
			compatible = "snps,dw-apb-timer";

			interrupts = <0 167 4>;

			reg = <0xffc08000 0x1000>;

			clocks = <&l4_sp_clk>;

			clock-names = "timer";

		};



		timer1: timer1@ffc09000 {

			compatible = "snps,dw-apb-timer";

			interrupts = <0 168 4>;

			reg = <0xffc09000 0x1000>;

			clocks = <&l4_sp_clk>;

			clock-names = "timer";

		};



		timer2: timer2@ffd00000 {

			compatible = "snps,dw-apb-timer";

			interrupts = <0 169 4>;

			reg = <0xffd00000 0x1000>;

			clocks = <&osc1>;

			clock-names = "timer";

		};



		timer3: timer3@ffd01000 {

			compatible = "snps,dw-apb-timer";

			interrupts = <0 170 4>;

			reg = <0xffd01000 0x1000>;

			clocks = <&osc1>;

			clock-names = "timer";

		};



		uart0: serial0@ffc02000 {
@@ -534,6 +610,7 @@ 
			interrupts = <0 162 4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&l4_sp_clk>;

		};



		uart1: serial1@ffc03000 {
@@ -542,13 +619,42 @@ 
			interrupts = <0 163 4>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&l4_sp_clk>;

		};



		rstmgr@ffd05000 {

		rst: rstmgr@ffd05000 {

			compatible = "altr,rst-mgr";

			reg = <0xffd05000 0x1000>;

		};



		usbphy0: usbphy@0 {

			#phy-cells = <0>;

			compatible = "usb-nop-xceiv";

			status = "okay";

		};



		usb0: usb@ffb00000 {

			compatible = "snps,dwc2";

			reg = <0xffb00000 0xffff>;

			interrupts = <0 125 4>;

			clocks = <&usb_mp_clk>;

			clock-names = "otg";

			phys = <&usbphy0>;

			phy-names = "usb2-phy";

			status = "disabled";

		};



		usb1: usb@ffb40000 {

			compatible = "snps,dwc2";

			reg = <0xffb40000 0xffff>;

			interrupts = <0 128 4>;

			clocks = <&usb_mp_clk>;

			clock-names = "otg";

			phys = <&usbphy0>;

			phy-names = "usb2-phy";

			status = "disabled";

		};



		sysmgr: sysmgr@ffd08000 {

			compatible = "altr,sys-mgr", "syscon";

			reg = <0xffd08000 0x4000>;

arch/arm/boot/dts/socfpga_arria5.dtsi

+1 −25
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
 */



/dts-v1/;

/include/ "socfpga.dtsi"

#include "socfpga.dtsi"



/ {

	soc {
@@ -38,32 +38,8 @@ 
			};

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};



		serial1@ffc03000 {

			clock-frequency = <100000000>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd080c4>;

		};



		timer0@ffc08000 {

			clock-frequency = <100000000>;

		};



		timer1@ffc09000 {

			clock-frequency = <100000000>;

		};



		timer2@ffd00000 {

			clock-frequency = <25000000>;

		};



		timer3@ffd01000 {

			clock-frequency = <25000000>;

		};

	};

};