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Commit 2b860db6 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Reserve ioctl numbers for set/get_caching 



I'm planing to merge this next week for 3.7, but I'd like to avoid
stupid conflicts with the exsting userspace when merging the new
reg_read ioctl (which doesn't have userspace yet, but this caching
interface has).

Header extracted from Chris Wilson's patch, but fix up the copy&pasted
comment in the interface struct.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7434a255

include/drm/i915_drm.h

+15 −0
Original line number Diff line number Diff line
@@ -203,6 +203,8 @@ typedef struct _drm_i915_sarea { 
#define DRM_I915_GEM_WAIT	0x2c

#define DRM_I915_GEM_CONTEXT_CREATE	0x2d

#define DRM_I915_GEM_CONTEXT_DESTROY	0x2e

#define DRM_I915_GEM_SET_CACHEING	0x2f

#define DRM_I915_GEM_GET_CACHEING	0x30



#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

#define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -227,6 +229,8 @@ typedef struct _drm_i915_sarea { 
#define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)

#define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)

#define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)

#define DRM_IOCTL_I915_GEM_SET_CACHEING		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)

#define DRM_IOCTL_I915_GEM_GET_CACHEING		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)

#define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)

#define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)

#define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
@@ -702,6 +706,17 @@ struct drm_i915_gem_busy { 
	__u32 busy;

};



#define I915_CACHEING_NONE		0

#define I915_CACHEING_CACHED		1



struct drm_i915_gem_cacheing {

	/** Handle of the buffer to check for busy */

	__u32 handle;



	/** Cacheing level to apply or return value */

	__u32 cacheing;

};



#define I915_TILING_NONE	0

#define I915_TILING_X		1

#define I915_TILING_Y		2