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Commit 2a419183 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
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drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for mmhub 



Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 89f99ceb

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+83 −94
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 


u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)

{

	u64 base = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE));

	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);



	base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;

	base <<= 24;
@@ -57,12 +57,10 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 
	value &= 0x0000FFFFFFFFF000ULL;

	value |= 0x1; /* valid bit */



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

		     lower_32_bits(value));



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

		     upper_32_bits(value));

}
@@ -70,18 +68,14 @@ static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 
{

	mmhub_v1_0_init_gart_pt_regs(adev);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

		     (u32)(adev->mc.gtt_start >> 12));

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

		     (u32)(adev->mc.gtt_start >> 44));



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

		     (u32)(adev->mc.gtt_end >> 12));

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

		     (u32)(adev->mc.gtt_end >> 44));

}
@@ -91,38 +85,34 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
	uint32_t tmp;



	/* Disable AGP. */

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);



	/* Program the system aperture low logical page number. */

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		     adev->mc.vram_start >> 18);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

		     adev->mc.vram_end >> 18);



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +

		adev->vm_manager.vram_base_offset;

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

		     (u32)(value >> 12));

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

		     (u32)(value >> 44));



	/* Program "protection fault". */

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),

	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

		     (u32)(adev->dummy_page.addr >> 12));

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),

	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

		     (u32)((u64)adev->dummy_page.addr >> 44));



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);

}



static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
@@ -130,7 +120,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 
	uint32_t tmp;



	/* Setup TLB control */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);



	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
@@ -143,7 +133,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 
			    MTYPE, MTYPE_UC);/* XXX for emulation. */

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);

}



static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
@@ -151,7 +141,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	uint32_t tmp;



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	/* XXX for emulation, Refer to closed source code.*/
@@ -160,49 +150,48 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);

}



static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)

{

	uint32_t tmp;



	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);

}



static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)

{

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

				mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

		     0XFFFFFFFF);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,

		     0x0000000F);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);

	WREG32_SOC15(MMHUB, 0,

		     mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);

	WREG32_SOC15(MMHUB, 0,

		     mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);



	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,

		     0);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,

		     0);

}



static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
@@ -266,9 +255,9 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 
		 * VF copy registers so vbios post doesn't program them, for

		 * SRIOV driver need to program them

		 */

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),

		WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,

			     adev->mc.vram_start >> 24);

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),

		WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,

			     adev->mc.vram_end >> 24);

	}
@@ -296,19 +285,19 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 
		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0);



	/* Setup TLB control */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

	tmp = REG_SET_FIELD(tmp,

				MC_VM_MX_L1_TLB_CNTL,

				ENABLE_ADVANCED_DRIVER_MODEL,

				0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);



	/* Setup L2 cache */

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), 0);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);

}



/**
@@ -320,7 +309,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 
void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)

{

	u32 tmp;

	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL));

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
@@ -345,7 +334,7 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 
			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);

}



void mmhub_v1_0_init(struct amdgpu_device *adev)
@@ -376,13 +365,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
{

	uint32_t def, data, def1, data1, def2 = 0, data2 = 0;



	def  = data  = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));

	def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);



	if (adev->asic_type != CHIP_RAVEN) {

		def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2));

		def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2));

		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

		def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);

	} else

		def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV));

		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {

		data |= ATC_L2_MISC_CG__ENABLE_MASK;
@@ -421,17 +410,17 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	}



	if (def != data)

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data);

		WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);



	if (def1 != data1) {

		if (adev->asic_type != CHIP_RAVEN)

			WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1);

			WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);

		else

			WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV), data1);

			WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);

	}



	if (adev->asic_type != CHIP_RAVEN && def2 != data2)

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2), data2);

		WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);

}



static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
@@ -439,7 +428,7 @@ static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
{

	uint32_t def, data;



	def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));

	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
@@ -447,7 +436,7 @@ static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;



	if (def != data)

		WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);

		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);

}



static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
@@ -455,7 +444,7 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
{

	uint32_t def, data;



	def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));

	def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

		data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
@@ -463,7 +452,7 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
		data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;



	if (def != data)

		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data);

		WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);

}



static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
@@ -471,7 +460,7 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
{

	uint32_t def, data;



	def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));

	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&

	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -480,7 +469,7 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;



	if(def != data)

		WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);

		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);

}



int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
@@ -516,12 +505,12 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 
		*flags = 0;



	/* AMD_CG_SUPPORT_MC_MGCG */

	data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));

	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)

		*flags |= AMD_CG_SUPPORT_MC_MGCG;



	/* AMD_CG_SUPPORT_MC_LS */

	data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));

	data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

	if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)

		*flags |= AMD_CG_SUPPORT_MC_LS;

}