Loading msm/vidc/msm_vidc_buffer_calculations.c +4 −2 Original line number Diff line number Diff line Loading @@ -1615,6 +1615,8 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, u32 output_mv_bufsize = 0, temp_scratch_mv_bufsize = 0; u32 size, bit_depth, num_LCUMB; u32 vpss_lineBufferSize_1 = 0; u32 width_mb_num = ((width + 15) >> 4); u32 height_mb_num = ((height + 15) >> 4); width_lcu_num = ((width)+(lcu_size)-1) / (lcu_size); height_lcu_num = ((height)+(lcu_size)-1) / (lcu_size); Loading Loading @@ -1680,8 +1682,8 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, BUFFER_ALIGNMENT_SIZE(32))); col_mv_buf_size = ALIGN(col_mv_buf_size, VENUS_DMA_ALIGNMENT) * (num_ref + 1); h265e_colrcbuf_size = (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); h265e_colrcbuf_size = (((width_mb_num + 7) >> 3) * 16 * 2 * height_mb_num); if (num_vpp_pipes > 1) h265e_colrcbuf_size = ALIGN(h265e_colrcbuf_size, VENUS_DMA_ALIGNMENT) * num_vpp_pipes; Loading msm/vidc/msm_vidc_platform.c +6 −9 Original line number Diff line number Diff line Loading @@ -90,12 +90,12 @@ static struct msm_vidc_codec_data kona_codec_data[] = { }; static struct msm_vidc_codec_data lagoon_codec_data[] = { CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 25, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 25, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 60, 200, 200), }; /* Update with SM6150 data */ Loading Loading @@ -2194,9 +2194,6 @@ void *vidc_get_drv_data(struct device *dev) ddr_type, driver_data->ubwc_config ? driver_data->ubwc_config->highest_bank_bit : -1); } else if (!strcmp(match->compatible, "qcom,bengal-vidc")) { d_vpr_h("Disable NOC error recovery"); msm_vidc_err_recovery_disable = VIDC_DISABLE_NOC_ERR_RECOV; rc = msm_vidc_read_rank(driver_data, dev); if (rc) { d_vpr_e("Failed to get ddr rank, use Dual Rank DDR\n"); Loading Loading
msm/vidc/msm_vidc_buffer_calculations.c +4 −2 Original line number Diff line number Diff line Loading @@ -1615,6 +1615,8 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, u32 output_mv_bufsize = 0, temp_scratch_mv_bufsize = 0; u32 size, bit_depth, num_LCUMB; u32 vpss_lineBufferSize_1 = 0; u32 width_mb_num = ((width + 15) >> 4); u32 height_mb_num = ((height + 15) >> 4); width_lcu_num = ((width)+(lcu_size)-1) / (lcu_size); height_lcu_num = ((height)+(lcu_size)-1) / (lcu_size); Loading Loading @@ -1680,8 +1682,8 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, BUFFER_ALIGNMENT_SIZE(32))); col_mv_buf_size = ALIGN(col_mv_buf_size, VENUS_DMA_ALIGNMENT) * (num_ref + 1); h265e_colrcbuf_size = (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); h265e_colrcbuf_size = (((width_mb_num + 7) >> 3) * 16 * 2 * height_mb_num); if (num_vpp_pipes > 1) h265e_colrcbuf_size = ALIGN(h265e_colrcbuf_size, VENUS_DMA_ALIGNMENT) * num_vpp_pipes; Loading
msm/vidc/msm_vidc_platform.c +6 −9 Original line number Diff line number Diff line Loading @@ -90,12 +90,12 @@ static struct msm_vidc_codec_data kona_codec_data[] = { }; static struct msm_vidc_codec_data lagoon_codec_data[] = { CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 25, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 25, 675, 320), CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 25, 200, 200), CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 60, 200, 200), }; /* Update with SM6150 data */ Loading Loading @@ -2194,9 +2194,6 @@ void *vidc_get_drv_data(struct device *dev) ddr_type, driver_data->ubwc_config ? driver_data->ubwc_config->highest_bank_bit : -1); } else if (!strcmp(match->compatible, "qcom,bengal-vidc")) { d_vpr_h("Disable NOC error recovery"); msm_vidc_err_recovery_disable = VIDC_DISABLE_NOC_ERR_RECOV; rc = msm_vidc_read_rank(driver_data, dev); if (rc) { d_vpr_e("Failed to get ddr rank, use Dual Rank DDR\n"); Loading