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Commit 29411f05 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: delete dead code of arbiter overdriver clk 



for sclk/mclk, can be adjusted through sysfs.
for uvd/vce clk, will be adjusted case by case when
requested.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 24562523

drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

+4 −25
Original line number Diff line number Diff line
@@ -728,9 +728,6 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) 


		if (clock < stable_pstate_sclk)

			clock = stable_pstate_sclk;

	} else {

		if (clock < hwmgr->gfx_arbiter.sclk)

			clock = hwmgr->gfx_arbiter.sclk;

	}



	if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
@@ -1085,14 +1082,8 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	uint32_t  num_of_active_displays = 0;

	struct cgs_display_info info = {0};



	cz_ps->evclk = hwmgr->vce_arbiter.evclk;

	cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;



	cz_ps->need_dfs_bypass = true;



	cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||

				hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);



	cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);



	clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
@@ -1105,9 +1096,6 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))

		clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;



	if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)

		clocks.memoryClock = hwmgr->gfx_arbiter.mclk;



	force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])

			|| (num_of_active_displays >= 3);
@@ -1339,22 +1327,13 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) 
				cz_hwmgr->vce_dpm.hard_min_clk,

				PPSMC_MSG_SetEclkHardMin));

	} else {

		/*Program HardMin based on the vce_arbiter.ecclk */

		if (hwmgr->vce_arbiter.ecclk == 0) {



		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetEclkHardMin, 0);

		/* disable ECLK DPM 0. Otherwise VCE could hang if

		 * switching SCLK from DPM 0 to 6/7 */

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetEclkSoftMin, 1);

		} else {

			cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;

			smum_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetEclkHardMin,

				cz_get_eclk_level(hwmgr,

					cz_hwmgr->vce_dpm.hard_min_clk,

					PPSMC_MSG_SetEclkHardMin));

		}

	}

	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c

+0 −34
Original line number Diff line number Diff line
@@ -159,7 +159,6 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr) 


static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)

{

	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);

	struct PP_Clocks clocks = {0};

	struct pp_display_clock_request clock_req;
@@ -170,39 +169,6 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) 
	PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),

				"Attempt to set DCF Clock Failed!", return -EINVAL);



	if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||

	    ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {

		rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;

		rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;

		smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetSoftMinVcn,

			(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);

	}



	if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&

		((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetHardMinSocclkByFreq,

					hwmgr->gfx_arbiter.sclk_hard_min / 100);

		rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);

	}



	if ((hwmgr->gfx_arbiter.gfxclk != 0) &&

		(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetMinVideoGfxclkFreq,

					hwmgr->gfx_arbiter.gfxclk / 100);

		rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);

	}



	if ((hwmgr->gfx_arbiter.fclk != 0) &&

		(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetMinVideoFclkFreq,

					hwmgr->gfx_arbiter.fclk / 100);

		rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);

	}



	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+0 −35
Original line number Diff line number Diff line
@@ -2722,9 +2722,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		}

	}



	smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;

	smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;



	cgs_get_active_displays_info(hwmgr->device, &info);



	minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
@@ -2754,38 +2751,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		minimum_clocks.memoryClock = stable_pstate_mclk;

	}



	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)

		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;



	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)

		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;



	smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;



	if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {

		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=

				hwmgr->platform_descriptor.overdriveLimit.engineClock),

				"Overdrive sclk exceeds limit",

				hwmgr->gfx_arbiter.sclk_over_drive =

						hwmgr->platform_descriptor.overdriveLimit.engineClock);



		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)

			smu7_ps->performance_levels[1].engine_clock =

					hwmgr->gfx_arbiter.sclk_over_drive;

	}



	if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {

		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=

				hwmgr->platform_descriptor.overdriveLimit.memoryClock),

				"Overdrive mclk exceeds limit",

				hwmgr->gfx_arbiter.mclk_over_drive =

						hwmgr->platform_descriptor.overdriveLimit.memoryClock);



		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)

			smu7_ps->performance_levels[1].memory_clock =

					hwmgr->gfx_arbiter.mclk_over_drive;

	}



	disable_mclk_switching_for_frame_lock = phm_cap_enabled(

				    hwmgr->platform_descriptor.platformCaps,

				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+1 −39
Original line number Diff line number Diff line
@@ -3124,9 +3124,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		}

	}



	vega10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;

	vega10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;



	cgs_get_active_displays_info(hwmgr->device, &info);



	/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
@@ -3165,38 +3162,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
		minimum_clocks.memoryClock = stable_pstate_mclk;

	}



	if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)

		minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;



	if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)

		minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;



	vega10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;



	if (hwmgr->gfx_arbiter.sclk_over_drive) {

		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=

				hwmgr->platform_descriptor.overdriveLimit.engineClock),

				"Overdrive sclk exceeds limit",

				hwmgr->gfx_arbiter.sclk_over_drive =

						hwmgr->platform_descriptor.overdriveLimit.engineClock);



		if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)

			vega10_ps->performance_levels[1].gfx_clock =

					hwmgr->gfx_arbiter.sclk_over_drive;

	}



	if (hwmgr->gfx_arbiter.mclk_over_drive) {

		PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=

				hwmgr->platform_descriptor.overdriveLimit.memoryClock),

				"Overdrive mclk exceeds limit",

				hwmgr->gfx_arbiter.mclk_over_drive =

						hwmgr->platform_descriptor.overdriveLimit.memoryClock);



		if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)

			vega10_ps->performance_levels[1].mem_clock =

					hwmgr->gfx_arbiter.mclk_over_drive;

	}



	disable_mclk_switching_for_frame_lock = phm_cap_enabled(

				    hwmgr->platform_descriptor.platformCaps,

				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
@@ -3819,10 +3784,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 
	uint32_t low_sclk_interrupt_threshold = 0;



	if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&

	    (hwmgr->gfx_arbiter.sclk_threshold !=

				data->low_sclk_interrupt_threshold)) {

		data->low_sclk_interrupt_threshold =

				hwmgr->gfx_arbiter.sclk_threshold;

		(data->low_sclk_interrupt_threshold != 0)) {

		low_sclk_interrupt_threshold =

				data->low_sclk_interrupt_threshold;

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+0 −34
Original line number Diff line number Diff line
@@ -105,36 +105,6 @@ struct phm_set_power_state_input { 
	const struct pp_hw_power_state *pnew_state;

};



struct phm_acp_arbiter {

	uint32_t acpclk;

};



struct phm_uvd_arbiter {

	uint32_t vclk;

	uint32_t dclk;

	uint32_t vclk_ceiling;

	uint32_t dclk_ceiling;

	uint32_t vclk_soft_min;

	uint32_t dclk_soft_min;

};



struct phm_vce_arbiter {

	uint32_t   evclk;

	uint32_t   ecclk;

};



struct phm_gfx_arbiter {

	uint32_t sclk;

	uint32_t sclk_hard_min;

	uint32_t mclk;

	uint32_t sclk_over_drive;

	uint32_t mclk_over_drive;

	uint32_t sclk_threshold;

	uint32_t num_cus;

	uint32_t gfxclk;

	uint32_t fclk;

};



struct phm_clock_array {

	uint32_t count;

	uint32_t values[1];
@@ -737,10 +707,6 @@ struct pp_hwmgr { 
	enum amd_dpm_forced_level dpm_level;

	enum amd_dpm_forced_level saved_dpm_level;

	enum amd_dpm_forced_level request_dpm_level;

	struct phm_gfx_arbiter gfx_arbiter;

	struct phm_acp_arbiter acp_arbiter;

	struct phm_uvd_arbiter uvd_arbiter;

	struct phm_vce_arbiter vce_arbiter;

	uint32_t usec_timeout;

	void *pptable;

	struct phm_platform_descriptor platform_descriptor;