Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2842e5bf authored by Joerg Roedel's avatar Joerg Roedel Committed by Ingo Molnar
Browse files

x86: move GART TLB flushing options to generic code 



The GART currently implements the iommu=[no]fullflush command line
parameters which influence its IO/TLB flushing strategy. This patch
makes these parameters generic so that they can be used by the AMD IOMMU
too.

Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 270cab24

Documentation/kernel-parameters.txt

+4 −0
Original line number Diff line number Diff line
@@ -893,6 +893,10 @@ and is between 256 and 4096 characters. It is defined in the file 
		nomerge

		forcesac

		soft

		fullflush

			Flush IO/TLB at every deallocation

		nofullflush

			Flush IO/TLB only when addresses are reused (default)





	intel_iommu=	[DMAR] Intel IOMMU driver (DMAR) option

Documentation/x86/x86_64/boot-options.txt

+0 −2
Original line number Diff line number Diff line
@@ -233,8 +233,6 @@ IOMMU (input/output memory management unit) 
  iommu options only relevant to the AMD GART hardware IOMMU:

    <size>             Set the size of the remapping area in bytes.

    allowed            Overwrite iommu off workarounds for specific chipsets.

    fullflush          Flush IOMMU on each allocation (default).

    nofullflush        Don't use IOMMU fullflush.

    leak               Turn on simple iommu leak tracing (only when

                       CONFIG_IOMMU_LEAK is on). Default number of leak pages

                       is 20.

arch/x86/kernel/pci-dma.c

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,15 @@ EXPORT_SYMBOL(dma_ops); 


static int iommu_sac_force __read_mostly;



/*

 * If this is disabled the IOMMU will use an optimized flushing strategy

 * of only flushing when an mapping is reused. With it true the GART is

 * flushed for every mapping. Problem is that doing the lazy flush seems

 * to trigger bugs with some popular PCI cards, in particular 3ware (but

 * has been also also seen with Qlogic at least).

 */

int iommu_fullflush;



#ifdef CONFIG_IOMMU_DEBUG

int panic_on_overflow __read_mostly = 1;

int force_iommu __read_mostly = 1;
@@ -171,6 +180,10 @@ static __init int iommu_setup(char *p) 
		}

		if (!strncmp(p, "nomerge", 7))

			iommu_merge = 0;

		if (!strncmp(p, "fullflush", 8))

			iommu_fullflush = 1;

		if (!strncmp(p, "nofullflush", 11))

			iommu_fullflush = 0;

		if (!strncmp(p, "forcesac", 8))

			iommu_sac_force = 1;

		if (!strncmp(p, "allowdac", 8))

arch/x86/kernel/pci-gart_64.c

+0 −13
Original line number Diff line number Diff line
@@ -45,15 +45,6 @@ static unsigned long iommu_pages; /* .. and in pages */ 


static u32 *iommu_gatt_base;		/* Remapping table */



/*

 * If this is disabled the IOMMU will use an optimized flushing strategy

 * of only flushing when an mapping is reused. With it true the GART is

 * flushed for every mapping. Problem is that doing the lazy flush seems

 * to trigger bugs with some popular PCI cards, in particular 3ware (but

 * has been also also seen with Qlogic at least).

 */

int iommu_fullflush = 1;



/* Allocation bitmap for the remapping area: */

static DEFINE_SPINLOCK(iommu_bitmap_lock);

/* Guarded by iommu_bitmap_lock: */
@@ -901,10 +892,6 @@ void __init gart_parse_options(char *p) 
#endif

	if (isdigit(*p) && get_option(&p, &arg))

		iommu_size = arg;

	if (!strncmp(p, "fullflush", 8))

		iommu_fullflush = 1;

	if (!strncmp(p, "nofullflush", 11))

		iommu_fullflush = 0;

	if (!strncmp(p, "noagp", 5))

		no_agp = 1;

	if (!strncmp(p, "noaperture", 10))

include/asm-x86/iommu.h

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ extern struct dma_mapping_ops nommu_dma_ops; 
extern int force_iommu, no_iommu;

extern int iommu_detected;

extern int dmar_disabled;

extern int iommu_fullflush;



extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);