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Commit 27a5bd64 authored by David Daney's avatar David Daney Committed by Ralf Baechle
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MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs 



Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/955/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6f329468

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -58,6 +58,9 @@ 
#define cpu_has_vint		0

#define cpu_has_vint		0

#define cpu_has_veic		0

#define cpu_has_veic		0

#define cpu_hwrena_impl_bits	0xc0000000

#define cpu_hwrena_impl_bits	0xc0000000



#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)



#define ARCH_HAS_READ_CURRENT_TIMER 1

#define ARCH_HAS_READ_CURRENT_TIMER 1

#define ARCH_HAS_IRQ_PER_CPU	1

#define ARCH_HAS_IRQ_PER_CPU	1

#define ARCH_HAS_SPINLOCK_PREFETCH 1

#define ARCH_HAS_SPINLOCK_PREFETCH 1