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Commit 278f1d07 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c updates from Wolfram Sang:
 "Highlights from the I2C subsystem for 3.18:

   - new drivers for Axxia AM55xx, and Hisilicon hix5hd2 SoC.

   - designware driver gained AMD support, exynos gained exynos7 support

  The rest is usual driver stuff.  Hopefully no lowlights this time"

* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: i801: Add Device IDs for Intel Sunrise Point PCH
  i2c: hix5hd2: add i2c controller driver
  i2c-imx: Disable the clock on probe failure
  i2c: designware: Add support for AMD I2C controller
  i2c: designware: Rework probe() to get clock a bit later
  i2c: designware: Default to fast mode in case of ACPI
  i2c: axxia: Add I2C driver for AXM55xx
  i2c: exynos: add support for HSI2C module on Exynos7
  i2c: mxs: detect No Slave Ack on SELECT in PIO mode
  i2c: cros_ec: Remove EC_I2C_FLAG_10BIT
  i2c: cros-ec-tunnel: Add of match table
  i2c: rcar: remove sign-compare flaw
  i2c: ismt: Use minimum descriptor size
  i2c: imx: Add arbitration lost check
  i2c: rk3x: Remove unlikely() annotations
  i2c: rcar: check for no IRQ in rcar_i2c_irq()
  i2c: rcar: make rcar_i2c_prepare_msg() *void*
  i2c: rcar: simplify check for last message
  i2c: designware: add support of platform data to set I2C mode
  i2c: designware: add support of I2C standard mode
parents d590c6cd 3e27a844

Documentation/devicetree/bindings/i2c/i2c-axxia.txt

0 → 100644
+30 −0
Original line number Diff line number Diff line 
LSI Axxia I2C



Required properties :

- compatible : Must be "lsi,api2c"

- reg : Offset and length of the register set for the device

- interrupts : the interrupt specifier

- #address-cells : Must be <1>;

- #size-cells : Must be <0>;

- clock-names : Must contain "i2c".

- clocks: Must contain an entry for each name in clock-names. See the common

  clock bindings.



Optional properties :

- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,

  the default 100 kHz frequency will be used. As only Normal and Fast modes

  are supported, possible values are 100000 and 400000.



Example :



i2c@02010084000 {

	compatible = "lsi,api2c";

	device_type = "i2c";

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x20 0x10084000 0x00 0x1000>;

	interrupts = <0 19 4>;

	clocks = <&clk_per>;

	clock-names = "i2c";

	clock-frequency = <400000>;

};

Documentation/devicetree/bindings/i2c/i2c-exynos5.txt

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ Required properties: 
				on Exynos5250 and Exynos5420 SoCs.

	-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available

				on Exynos5260 SoCs.

	-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available

				on Exynos7 SoCs.



  - reg: physical base address of the controller and length of memory mapped

    region.

Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt

0 → 100644
+24 −0
Original line number Diff line number Diff line 
I2C for Hisilicon hix5hd2 chipset platform



Required properties:

- compatible: Must be "hisilicon,hix5hd2-i2c"

- reg: physical base address of the controller and length of memory mapped

     region.

- interrupts: interrupt number to the cpu.

- #address-cells = <1>;

- #size-cells = <0>;

- clocks: phandles to input clocks.



Optional properties:

- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000

- Child nodes conforming to i2c bus binding



Examples:

I2C0@f8b10000 {

	compatible = "hisilicon,hix5hd2-i2c";

	reg = <0xf8b10000 0x1000>;

	interrupts = <0 38 4>;

	clocks = <&clock HIX5HD2_I2C0_RST>;

	#address-cells = <1>;

	#size-cells = <0>;

}

Documentation/i2c/busses/i2c-i801

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ Supported adapters: 
  * Intel Wildcat Point (PCH)

  * Intel Wildcat Point-LP (PCH)

  * Intel BayTrail (SOC)

  * Intel Sunrise Point-H (PCH)

   Datasheets: Publicly available at the Intel website



On Intel Patsburg and later chipsets, both the normal host SMBus controller

drivers/i2c/busses/Kconfig

+24 −1
Original line number Diff line number Diff line
@@ -77,6 +77,16 @@ config I2C_AMD8111 
	  This driver can also be built as a module.  If so, the module

	  will be called i2c-amd8111.



config I2C_HIX5HD2

	tristate "Hix5hd2 high-speed I2C driver"

	depends on ARCH_HIX5HD2

	help

	  Say Y here to include support for high-speed I2C controller in the

	  Hisilicon based hix5hd2 SoCs.



	  This driver can also be built as a module.  If so, the module

	  will be called i2c-hix5hd2.



config I2C_I801

	tristate "Intel 82801 (ICH/PCH)"

	depends on PCI
@@ -112,6 +122,7 @@ config I2C_I801 
	    Wildcat Point (PCH)

	    Wildcat Point-LP (PCH)

	    BayTrail (SOC)

	    Sunrise Point-H (PCH)



	  This driver can also be built as a module.  If so, the module

	  will be called i2c-i801.
@@ -337,6 +348,17 @@ config I2C_AU1550 
	  This driver can also be built as a module.  If so, the module

	  will be called i2c-au1550.



config I2C_AXXIA

	tristate "Axxia I2C controller"

	depends on ARCH_AXXIA || COMPILE_TEST

	default ARCH_AXXIA

	help

	  Say yes if you want to support the I2C bus on Axxia platforms.



	  Please note that this controller is limited to transfers of maximum

	  255 bytes in length. Any attempt to to a larger transfer will return

	  an error.



config I2C_BCM2835

	tristate "Broadcom BCM2835 I2C controller"

	depends on ARCH_BCM2835
@@ -423,6 +445,7 @@ config I2C_DESIGNWARE_CORE 
config I2C_DESIGNWARE_PLATFORM

	tristate "Synopsys DesignWare Platform"

	select I2C_DESIGNWARE_CORE

	depends on (ACPI && COMMON_CLK) || !ACPI

	help

	  If you say yes to this option, support will be included for the

	  Synopsys DesignWare I2C adapter. Only master mode is supported.
@@ -465,7 +488,7 @@ config I2C_EG20T 


config I2C_EXYNOS5

	tristate "Exynos5 high-speed I2C driver"

	depends on ARCH_EXYNOS5 && OF

	depends on ARCH_EXYNOS && OF

	default y

	help

	  High-speed I2C controller on Exynos5 based Samsung SoCs.