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Commit 278b45b0 authored by Andrew Lunn's avatar Andrew Lunn
Browse files

ARM: Orion: DT support for IRQ and GPIO Controllers 



Both IRQ and GPIO controllers can now be represented in DT.  The IRQ
controllers are setup first, and then the GPIO controllers. Interrupts
for GPIO lines are placed directly after the main interrupts in the
interrupt space.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Tested-by: default avatarJosh Coombs <josh.coombs@gmail.com>
Tested-by: default avatarSimon Baatz <gmbnomis@gmail.com>
parent 89fb2d77

Documentation/devicetree/bindings/arm/mrvl/intc.txt

+20 −0
Original line number Diff line number Diff line
@@ -38,3 +38,23 @@ Example: 
		reg-names = "mux status", "mux mask";

		mrvl,intc-nr-irqs = <2>;

	};



* Marvell Orion Interrupt controller



Required properties

- compatible :  Should be "marvell,orion-intc".

- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. Supported value is <1>.

- interrupt-controller : Declare this node to be an interrupt controller.

- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.

        One entry in the list represents 32 interrupts.



Example:



	intc: interrupt-controller {

        	compatible = "marvell,orion-intc", "marvell,intc";

		interrupt-controller;

		#interrupt-cells = <1>;

                reg = <0xfed20204 0x04>,

		      <0xfed20214 0x04>;

        };

Documentation/devicetree/bindings/gpio/mrvl-gpio.txt

+23 −0
Original line number Diff line number Diff line
@@ -27,3 +27,26 @@ Example: 
		interrupt-controller;

		#interrupt-cells = <1>;

      };



* Marvell Orion GPIO Controller



Required properties:

- compatible         : Should be "marvell,orion-gpio"

- reg                : Address and length of the register set for controller.

- gpio-controller    : So we know this is a gpio controller.

- ngpio              : How many gpios this controller has.

- interrupts	     : Up to 4 Interrupts for the controller.



Optional properties:

- mask-offset        : For SMP Orions, offset for Nth CPU



Example:



		gpio0: gpio@10100 {

			compatible = "marvell,orion-gpio";

			#gpio-cells = <2>;

			gpio-controller;

			reg = <0x10100 0x40>;

			ngpio = <32>;

			interrupts = <35>, <36>, <37>, <38>;

		};

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -1105,6 +1105,7 @@ config PLAT_ORION 
	bool

	select CLKSRC_MMIO

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN

	select COMMON_CLK



config PLAT_PXA

arch/arm/boot/dts/kirkwood.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -2,6 +2,15 @@ 


/ {

	compatible = "marvell,kirkwood";

	interrupt-parent = <&intc>;



	intc: interrupt-controller {

		compatible = "marvell,orion-intc", "marvell,intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xf1020204 0x04>,

		      <0xf1020214 0x04>;

	};



	ocp@f1000000 {

		compatible = "simple-bus";
@@ -9,6 +18,24 @@ 
		#address-cells = <1>;

		#size-cells = <1>;



		gpio0: gpio@10100 {

			compatible = "marvell,orion-gpio";

			#gpio-cells = <2>;

			gpio-controller;

			reg = <0x10100 0x40>;

			ngpio = <32>;

			interrupts = <35>, <36>, <37>, <38>;

		};



		gpio1: gpio@10140 {

			compatible = "marvell,orion-gpio";

			#gpio-cells = <2>;

			gpio-controller;

			reg = <0x10140 0x40>;

			ngpio = <18>;

			interrupts = <39>, <40>, <41>;

		};



		serial@12000 {

			compatible = "ns16550a";

			reg = <0x12000 0x100>;

arch/arm/mach-dove/irq.c

+29 −29
Original line number Diff line number Diff line
@@ -20,22 +20,6 @@ 
#include <mach/bridge-regs.h>

#include "common.h"



static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)

{

	int irqoff;

	BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);



	irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :

		3 + irq - IRQ_DOVE_GPIO_24_31;



	orion_gpio_irq_handler(irqoff << 3);

	if (irq == IRQ_DOVE_HIGH_GPIO) {

		orion_gpio_irq_handler(40);

		orion_gpio_irq_handler(48);

		orion_gpio_irq_handler(56);

	}

}



static void pmu_irq_mask(struct irq_data *d)

{

	int pin = irq_to_pmu(d->irq);
@@ -90,6 +74,27 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) 
	}

}



static int __initdata gpio0_irqs[4] = {

	IRQ_DOVE_GPIO_0_7,

	IRQ_DOVE_GPIO_8_15,

	IRQ_DOVE_GPIO_16_23,

	IRQ_DOVE_GPIO_24_31,

};



static int __initdata gpio1_irqs[4] = {

	IRQ_DOVE_HIGH_GPIO,

	0,

	0,

	0,

};



static int __initdata gpio2_irqs[4] = {

	0,

	0,

	0,

	0,

};



void __init dove_init_irq(void)

{

	int i;
@@ -100,19 +105,14 @@ void __init dove_init_irq(void) 
	/*

	 * Initialize gpiolib for GPIOs 0-71.

	 */

	orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START);

	irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);

	irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);

	irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);

	irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);



	orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 32);

	irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);



	orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 64);

	orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START, gpio0_irqs);



	orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 32, gpio1_irqs);



	orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,

			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);



	/*

	 * Mask and clear PMU interrupts