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Commit 272b9161 authored by David Collins's avatar David Collins
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dt-bindings: clock: Add NPU clock controller device bindings for KONA 



Add binding documentation for the KONA NPU clock controller.
Also update the npucc header file to remove the npu_cc_aon_clk
which should not be modified by software.

Change-Id: I5002cc61c81fb696fc69c438a2d71cba28e61f16
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent a5d4d558

Documentation/devicetree/bindings/clock/qcom,npucc.txt

0 → 100644
+26 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. NPU Clock & Reset Controller Bindings

-----------------------------------------------------------------



Required properties :

- compatible:		Should be "qcom,npucc-kona".

- reg:			Shall contain base register addresses and sizes.

- reg-names:		Names of the register bases listed in the same order as

			in the reg property.  Shall include: "cc", "qdsp6ss",

			and "qdsp6ss_pll".

- vdd_cx-supply:	Phandle of the VDD_CX regulator supply rail that needs

			to be voted on behalf of the NPU CC clocks.

- #clock-cells:		Shall contain 1.

- #reset-cells:		Shall contain 1.



Example:



clock_npucc: qcom,npucc@9980000 {

	compatible = "qcom,npucc-kona";

	reg = <0x9980000 0x10000>,

		<0x9800000 0x10000>,

		<0x9810000 0x10000>;

	reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";

	vdd_cx-supply = <&VDD_CX_LEVEL>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

include/dt-bindings/clock/qcom,npucc-kona.h

+48 −46
Original line number Diff line number Diff line
@@ -4,57 +4,59 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_KONA_H

#define _DT_BINDINGS_CLK_QCOM_NPU_CC_KONA_H



#define NPU_CC_AON_CLK						0

#define NPU_CC_ATB_CLK						1

#define NPU_CC_BTO_CORE_CLK					2

#define NPU_CC_BWMON_CLK					3

#define NPU_CC_CAL_HM0_CDC_CLK					4

#define NPU_CC_CAL_HM0_CLK					5

#define NPU_CC_CAL_HM0_CLK_SRC					6

#define NPU_CC_CAL_HM0_DPM_IP_CLK				7

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				8

#define NPU_CC_CAL_HM1_CDC_CLK					9

#define NPU_CC_CAL_HM1_CLK					10

#define NPU_CC_CAL_HM1_CLK_SRC					11

#define NPU_CC_CAL_HM1_DPM_IP_CLK				12

#define NPU_CC_CAL_HM1_PERF_CNT_CLK				13

#define NPU_CC_CORE_CLK						14

#define NPU_CC_CORE_CLK_SRC					15

#define NPU_CC_DL_DPM_CLK					16

#define NPU_CC_DL_LLM_CLK					17

#define NPU_CC_DPM_CLK						18

#define NPU_CC_DPM_TEMP_CLK					19

#define NPU_CC_DPM_XO_CLK					20

#define NPU_CC_DSP_AHBM_CLK					21

#define NPU_CC_DSP_AHBS_CLK					22

#define NPU_CC_DSP_AXI_CLK					23

#define NPU_CC_DSP_BWMON_AHB_CLK				24

#define NPU_CC_DSP_BWMON_CLK					25

#define NPU_CC_ISENSE_CLK					26

#define NPU_CC_LLM_CLK						27

#define NPU_CC_LLM_CURR_CLK					28

#define NPU_CC_LLM_TEMP_CLK					29

#define NPU_CC_LLM_XO_CLK					30

#define NPU_CC_LMH_CLK_SRC					31

#define NPU_CC_NOC_AHB_CLK					32

#define NPU_CC_NOC_AXI_CLK					33

#define NPU_CC_NOC_DMA_CLK					34

#define NPU_CC_PLL0						35

#define NPU_CC_PLL0_OUT_EVEN					36

#define NPU_CC_PLL1						37

#define NPU_CC_PLL1_OUT_EVEN					38

#define NPU_CC_RSC_XO_CLK					39

#define NPU_CC_S2P_CLK						40

#define NPU_CC_XO_CLK						41

#define NPU_CC_XO_CLK_SRC					42

#define NPU_DSP_CORE_CLK_SRC					43

#define NPU_Q6SS_PLL						44

#define NPU_CC_ATB_CLK						0

#define NPU_CC_BTO_CORE_CLK					1

#define NPU_CC_BWMON_CLK					2

#define NPU_CC_CAL_HM0_CDC_CLK					3

#define NPU_CC_CAL_HM0_CLK					4

#define NPU_CC_CAL_HM0_CLK_SRC					5

#define NPU_CC_CAL_HM0_DPM_IP_CLK				6

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				7

#define NPU_CC_CAL_HM1_CDC_CLK					8

#define NPU_CC_CAL_HM1_CLK					9

#define NPU_CC_CAL_HM1_CLK_SRC					10

#define NPU_CC_CAL_HM1_DPM_IP_CLK				11

#define NPU_CC_CAL_HM1_PERF_CNT_CLK				12

#define NPU_CC_CORE_CLK						13

#define NPU_CC_CORE_CLK_SRC					14

#define NPU_CC_DL_DPM_CLK					15

#define NPU_CC_DL_LLM_CLK					16

#define NPU_CC_DPM_CLK						17

#define NPU_CC_DPM_TEMP_CLK					18

#define NPU_CC_DPM_XO_CLK					19

#define NPU_CC_DSP_AHBM_CLK					20

#define NPU_CC_DSP_AHBS_CLK					21

#define NPU_CC_DSP_AXI_CLK					22

#define NPU_CC_DSP_BWMON_AHB_CLK				23

#define NPU_CC_DSP_BWMON_CLK					24

#define NPU_CC_ISENSE_CLK					25

#define NPU_CC_LLM_CLK						26

#define NPU_CC_LLM_CURR_CLK					27

#define NPU_CC_LLM_TEMP_CLK					28

#define NPU_CC_LLM_XO_CLK					29

#define NPU_CC_LMH_CLK_SRC					30

#define NPU_CC_NOC_AHB_CLK					31

#define NPU_CC_NOC_AXI_CLK					32

#define NPU_CC_NOC_DMA_CLK					33

#define NPU_CC_PLL0						34

#define NPU_CC_PLL0_OUT_EVEN					35

#define NPU_CC_PLL1						36

#define NPU_CC_PLL1_OUT_EVEN					37

#define NPU_CC_RSC_XO_CLK					38

#define NPU_CC_S2P_CLK						39

#define NPU_CC_XO_CLK						40

#define NPU_CC_XO_CLK_SRC					41

#define NPU_DSP_CORE_CLK_SRC					42

#define NPU_Q6SS_PLL						43



#define CORE_GDSC						0



#define NPU_CC_CAL_HM0_BCR					0

#define NPU_CC_CAL_HM1_BCR					1

#define NPU_CC_CORE_BCR						2

#define NPU_CC_DSP_BCR						3

#define NPU_CC_DPM_TEMP_CLK_ARES				3

#define NPU_CC_DSP_BCR						4

#define NPU_CC_LLM_CURR_CLK_ARES				5

#define NPU_CC_LLM_TEMP_CLK_ARES				6



#endif