Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26b9c4a5 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Remove the explicit flush of the GPU write domain 



Rely instead on the insertion of the implicit flush before the seqno
breadcrumb.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 86d5bc37

drivers/gpu/drm/i915/i915_gem.c

+0 −34
Original line number Original line Diff line number Diff line
@@ -37,7 +37,6 @@ 
#include <linux/pci.h>

#include <linux/pci.h>

#include <linux/dma-buf.h>

#include <linux/dma-buf.h>





static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);

static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);

static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);

static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);

static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);

static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,

static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
@@ -2021,10 +2020,6 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj) 
	int ret;

	int ret;





	if (obj->active) {

	if (obj->active) {

		ret = i915_gem_object_flush_gpu_write_domain(obj);

		if (ret)

			return ret;



		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);

		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);

		if (ret)

		if (ret)

			return ret;

			return ret;
@@ -2782,17 +2777,6 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj) 
	drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);

	drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);

}

}





/** Flushes any GPU write domain for the object if it's dirty. */

static int

i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)

{

	if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)

		return 0;



	/* Queue the GPU write cache flushing we need. */

	return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);

}



/** Flushes the GTT write domain for the object if it's dirty. */

/** Flushes the GTT write domain for the object if it's dirty. */

static void

static void

i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)

i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
@@ -2859,10 +2843,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)

	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)

		return 0;

		return 0;





	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret)

		return ret;



	ret = i915_gem_object_wait_rendering(obj, !write);

	ret = i915_gem_object_wait_rendering(obj, !write);

	if (ret)

	if (ret)

		return ret;

		return ret;
@@ -2973,10 +2953,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 
	u32 old_read_domains, old_write_domain;

	u32 old_read_domains, old_write_domain;

	int ret;

	int ret;





	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret)

		return ret;



	if (pipelined != obj->ring) {

	if (pipelined != obj->ring) {

		ret = i915_gem_object_sync(obj, pipelined);

		ret = i915_gem_object_sync(obj, pipelined);

		if (ret)

		if (ret)
@@ -3030,12 +3006,6 @@ i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) 
	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)

	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)

		return 0;

		return 0;





	if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {

		ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);

		if (ret)

			return ret;

	}



	ret = i915_gem_object_wait_rendering(obj, false);

	ret = i915_gem_object_wait_rendering(obj, false);

	if (ret)

	if (ret)

		return ret;

		return ret;
@@ -3060,10 +3030,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)

	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)

		return 0;

		return 0;





	ret = i915_gem_object_flush_gpu_write_domain(obj);

	if (ret)

		return ret;



	ret = i915_gem_object_wait_rendering(obj, !write);

	ret = i915_gem_object_wait_rendering(obj, !write);

	if (ret)

	if (ret)

		return ret;

		return ret;