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Commit 269fe32d authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/bar: swap oneinit/init ordering, and rename bar3 to bar2 



NVIDIA call it BAR2, Linux APIs treat it as BAR3 due to BAR1 being a
64-bit BAR, which I presume take two slots or something.

No actual code changes here, just to make future commits less messy.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c9e70592

drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c

+5 −5
Original line number Diff line number Diff line
@@ -46,18 +46,18 @@ nvkm_bar_umap(struct nvkm_bar *bar, u64 size, int type, struct nvkm_vma *vma) 
}



static int

nvkm_bar_oneinit(struct nvkm_subdev *subdev)

nvkm_bar_init(struct nvkm_subdev *subdev)

{

	struct nvkm_bar *bar = nvkm_bar(subdev);

	return bar->func->oneinit(bar);

	bar->func->init(bar);

	return 0;

}



static int

nvkm_bar_init(struct nvkm_subdev *subdev)

nvkm_bar_oneinit(struct nvkm_subdev *subdev)

{

	struct nvkm_bar *bar = nvkm_bar(subdev);

	bar->func->init(bar);

	return 0;

	return bar->func->oneinit(bar);

}



static void *

drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c

+24 −24
Original line number Diff line number Diff line
@@ -41,8 +41,26 @@ gf100_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma) 
	return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);

}



void

gf100_bar_init(struct nvkm_bar *base)

{

	struct gf100_bar *bar = gf100_bar(base);

	struct nvkm_device *device = bar->base.subdev.device;

	u32 addr;



	addr = nvkm_memory_addr(bar->bar[1].mem) >> 12;

	nvkm_wr32(device, 0x001704, 0x80000000 | addr);



	if (bar->bar[0].mem) {

		addr = nvkm_memory_addr(bar->bar[0].mem) >> 12;

		if (bar->bar2_halve)

			addr |= 0x40000000;

		nvkm_wr32(device, 0x001714, 0x80000000 | addr);

	}

}



static int

gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,

gf100_bar_oneinit_bar(struct gf100_bar *bar, struct gf100_barN *bar_vm,

		      struct lock_class_key *key, int bar_nr)

{

	struct nvkm_device *device = bar->base.subdev.device;
@@ -98,43 +116,25 @@ int 
gf100_bar_oneinit(struct nvkm_bar *base)

{

	static struct lock_class_key bar1_lock;

	static struct lock_class_key bar3_lock;

	static struct lock_class_key bar2_lock;

	struct gf100_bar *bar = gf100_bar(base);

	int ret;



	/* BAR3 */

	/* BAR2 */

	if (bar->base.func->kmap) {

		ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3);

		ret = gf100_bar_oneinit_bar(bar, &bar->bar[0], &bar2_lock, 3);

		if (ret)

			return ret;

	}



	/* BAR1 */

	ret = gf100_bar_ctor_vm(bar, &bar->bar[1], &bar1_lock, 1);

	ret = gf100_bar_oneinit_bar(bar, &bar->bar[1], &bar1_lock, 1);

	if (ret)

		return ret;



	return 0;

}



void

gf100_bar_init(struct nvkm_bar *base)

{

	struct gf100_bar *bar = gf100_bar(base);

	struct nvkm_device *device = bar->base.subdev.device;

	u32 addr;



	addr = nvkm_memory_addr(bar->bar[1].mem) >> 12;

	nvkm_wr32(device, 0x001704, 0x80000000 | addr);



	if (bar->bar[0].mem) {

		addr = nvkm_memory_addr(bar->bar[0].mem) >> 12;

		if (bar->bar2_halve)

			addr |= 0x40000000;

		nvkm_wr32(device, 0x001714, 0x80000000 | addr);

	}

}



void *

gf100_bar_dtor(struct nvkm_bar *base)

{

drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h

+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
#define gf100_bar(p) container_of((p), struct gf100_bar, base)

#include "priv.h"



struct gf100_bar_vm {

struct gf100_barN {

	struct nvkm_memory *mem;

	struct nvkm_gpuobj *pgd;

	struct nvkm_vm *vm;
@@ -12,7 +12,7 @@ struct gf100_bar_vm { 
struct gf100_bar {

	struct nvkm_bar base;

	bool bar2_halve;

	struct gf100_bar_vm bar[2];

	struct gf100_barN bar[2];

};



int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,

drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c

+33 −33
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
struct nvkm_vm *

nv50_bar_kmap(struct nvkm_bar *base)

{

	return nv50_bar(base)->bar3_vm;

	return nv50_bar(base)->bar2_vm;

}



int
@@ -56,13 +56,28 @@ nv50_bar_flush(struct nvkm_bar *base) 
	spin_unlock_irqrestore(&bar->base.lock, flags);

}



void

nv50_bar_init(struct nvkm_bar *base)

{

	struct nv50_bar *bar = nv50_bar(base);

	struct nvkm_device *device = bar->base.subdev.device;

	int i;



	nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);

	nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);

	nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);

	nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);

	for (i = 0; i < 8; i++)

		nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);

}



int

nv50_bar_oneinit(struct nvkm_bar *base)

{

	struct nv50_bar *bar = nv50_bar(base);

	struct nvkm_device *device = bar->base.subdev.device;

	static struct lock_class_key bar1_lock;

	static struct lock_class_key bar3_lock;

	static struct lock_class_key bar2_lock;

	struct nvkm_vm *vm;

	u64 start, limit;

	int ret;
@@ -80,11 +95,11 @@ nv50_bar_oneinit(struct nvkm_bar *base) 
	if (ret)

		return ret;



	/* BAR3 */

	/* BAR2 */

	start = 0x0100000000ULL;

	limit = start + device->func->resource_size(device, 3);



	ret = nvkm_vm_new(device, start, limit - start, start, &bar3_lock, &vm);

	ret = nvkm_vm_new(device, start, limit - start, start, &bar2_lock, &vm);

	if (ret)

		return ret;
@@ -94,24 +109,24 @@ nv50_bar_oneinit(struct nvkm_bar *base) 
	if (ret)

		return ret;



	ret = nvkm_vm_ref(vm, &bar->bar3_vm, bar->pgd);

	ret = nvkm_vm_ref(vm, &bar->bar2_vm, bar->pgd);

	nvkm_vm_ref(NULL, &vm, NULL);

	if (ret)

		return ret;



	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar3);

	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2);

	if (ret)

		return ret;



	nvkm_kmap(bar->bar3);

	nvkm_wo32(bar->bar3, 0x00, 0x7fc00000);

	nvkm_wo32(bar->bar3, 0x04, lower_32_bits(limit));

	nvkm_wo32(bar->bar3, 0x08, lower_32_bits(start));

	nvkm_wo32(bar->bar3, 0x0c, upper_32_bits(limit) << 24 |

	nvkm_kmap(bar->bar2);

	nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);

	nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));

	nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));

	nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |

				   upper_32_bits(start));

	nvkm_wo32(bar->bar3, 0x10, 0x00000000);

	nvkm_wo32(bar->bar3, 0x14, 0x00000000);

	nvkm_done(bar->bar3);

	nvkm_wo32(bar->bar2, 0x10, 0x00000000);

	nvkm_wo32(bar->bar2, 0x14, 0x00000000);

	nvkm_done(bar->bar2);



	/* BAR1 */

	start = 0x0000000000ULL;
@@ -144,31 +159,16 @@ nv50_bar_oneinit(struct nvkm_bar *base) 
	return 0;

}



void

nv50_bar_init(struct nvkm_bar *base)

{

	struct nv50_bar *bar = nv50_bar(base);

	struct nvkm_device *device = bar->base.subdev.device;

	int i;



	nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);

	nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);

	nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);

	nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4);

	for (i = 0; i < 8; i++)

		nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);

}



void *

nv50_bar_dtor(struct nvkm_bar *base)

{

	struct nv50_bar *bar = nv50_bar(base);

	nvkm_gpuobj_del(&bar->bar1);

	nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);

	nvkm_gpuobj_del(&bar->bar3);

	if (bar->bar3_vm) {

		nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);

		nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);

	nvkm_gpuobj_del(&bar->bar2);

	if (bar->bar2_vm) {

		nvkm_memory_del(&bar->bar2_vm->pgt[0].mem[0]);

		nvkm_vm_ref(NULL, &bar->bar2_vm, bar->pgd);

	}

	nvkm_gpuobj_del(&bar->pgd);

	nvkm_gpuobj_del(&bar->pad);

drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h

+2 −2
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ struct nv50_bar { 
	struct nvkm_gpuobj *pgd;

	struct nvkm_vm *bar1_vm;

	struct nvkm_gpuobj *bar1;

	struct nvkm_vm *bar3_vm;

	struct nvkm_gpuobj *bar3;

	struct nvkm_vm *bar2_vm;

	struct nvkm_gpuobj *bar2;

};



int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,