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Commit 264ff016 authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan Committed by Jani Nikula
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drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails 



Noticed that we assume the best case of 0 latency when the DPCD read
fails, reasonable pessimism is safer.

eDP spec does say that if latency is greater than 8, the panel
supplier needs to provide it. I didn't see anything specific in the VBT
for this, so let's go with 8 frames as a fallback.

Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511195145.3829-5-dhinakaran.pandiyan@intel.com
parent 1e8b251e

drivers/gpu/drm/i915/intel_psr.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -219,13 +219,13 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 




static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

{

{

	u8 val = 0;

	u8 val = 8; /* assume the worst if we can't read the value */





	if (drm_dp_dpcd_readb(&intel_dp->aux,

	if (drm_dp_dpcd_readb(&intel_dp->aux,

			      DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)

			      DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)

		val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;

		val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;

	else

	else

		DRM_ERROR("Unable to get sink synchronization latency\n");

		DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");

	return val;

	return val;

}

}