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Commit 26045b53 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2014-11-21-fixed' of... 

Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next

drm-intel-next-2014-11-21:
- infoframe tracking (for fastboot) from Jesse
- start of the dri1/ums support removal
- vlv forcewake timeout fixes (Imre)
- bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom
  O'Rourke)
- on-demand pinning for execlist contexts
- vlv/chv backlight improvements (Ville)
- gen8+ render ctx w/a work from various people
- skl edp programming (Satheeshakrishna et al.)
- psr docbook (Rodrigo)
- piles of little fixes and improvements all over, as usual

* tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits)
  drm/i915: Don't pin LRC in GGTT when dumping in debugfs
  drm/i915: Update DRIVER_DATE to 20141121
  drm/i915/g4x: fix g4x infoframe readout
  drm/i915: Only call mod_timer() if not already pending
  drm/i915: Don't rely upon encoder->type for infoframe hw state readout
  drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave
  drm/i915: Use ggtt error obj capture helper for gen8 semaphores
  drm/i915: vlv: increase timeout when setting idle GPU freq
  drm/i915: vlv: fix cdclk setting during modeset while suspended
  drm/i915: Dump hdmi pipe_config state
  drm/i915: Gen9 shadowed registers
  drm/i915/skl: Gen9 multi-engine forcewake
  drm/i915: Read power well status before other registers for drpc info
  drm/i915: Pin tiled objects for L-shaped configs
  drm/i915: Update ring freq for full gpu freq range
  drm/i915: change initial rps frequency for gen8
  drm/i915: Keep min freq above floor on HSW/BDW
  drm/i915: Use efficient frequency for HSW/BDW
  drm/i915: Can i915_gem_init_ioctl
  drm/i915: Sanitize ->lastclose
  ...
parents 1a92b7a2 064ca1d2

Documentation/DocBook/drm.tmpl

+26 −0
Original line number Diff line number Diff line
@@ -3919,6 +3919,11 @@ int num_ioctls;</synopsis> 
	<title>High Definition Audio</title>

!Pdrivers/gpu/drm/i915/intel_audio.c High Definition Audio over HDMI and Display Port

!Idrivers/gpu/drm/i915/intel_audio.c

      </sect2>

      <sect2>

	<title>Panel Self Refresh PSR (PSR/SRD)</title>

!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD)

!Idrivers/gpu/drm/i915/intel_psr.c

      </sect2>

      <sect2>

        <title>DPIO</title>
@@ -4029,6 +4034,27 @@ int num_ioctls;</synopsis> 
!Idrivers/gpu/drm/i915/intel_lrc.c

      </sect2>

    </sect1>



    <sect1>

      <title> Tracing </title>

      <para>

    This sections covers all things related to the tracepoints implemented in

    the i915 driver.

      </para>

      <sect2>

        <title> i915_ppgtt_create and i915_ppgtt_release </title>

!Pdrivers/gpu/drm/i915/i915_trace.h i915_ppgtt_create and i915_ppgtt_release tracepoints

      </sect2>

      <sect2>

        <title> i915_context_create and i915_context_free </title>

!Pdrivers/gpu/drm/i915/i915_trace.h i915_context_create and i915_context_free tracepoints

      </sect2>

      <sect2>

        <title> switch_mm </title>

!Pdrivers/gpu/drm/i915/i915_trace.h switch_mm tracepoint

      </sect2>

    </sect1>



  </chapter>

!Cdrivers/gpu/drm/i915/i915_irq.c

</part>

drivers/gpu/drm/drm_edid.c

+5 −2
Original line number Diff line number Diff line
@@ -3145,9 +3145,12 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 
		}

	}

	eld[5] |= sad_count << 4;

	eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;



	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);

	eld[DRM_ELD_BASELINE_ELD_LEN] =

		DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);



	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",

		      drm_eld_size(eld), sad_count);

}

EXPORT_SYMBOL(drm_edid_to_eld);

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ i915-y += intel_audio.o \ 
	  intel_frontbuffer.o \

	  intel_modes.o \

	  intel_overlay.o \

	  intel_psr.o \

	  intel_sideband.o \

	  intel_sprite.o

i915-$(CONFIG_ACPI)		+= intel_acpi.o intel_opregion.o

drivers/gpu/drm/i915/i915_cmd_parser.c

+5 −1
Original line number Diff line number Diff line
@@ -413,6 +413,8 @@ static const u32 gen7_render_regs[] = { 
	REG64(PS_INVOCATION_COUNT),

	REG64(PS_DEPTH_COUNT),

	OACONTROL, /* Only allowed for LRI and SRM. See below. */

	REG64(MI_PREDICATE_SRC0),

	REG64(MI_PREDICATE_SRC1),

	GEN7_3DPRIM_END_OFFSET,

	GEN7_3DPRIM_START_VERTEX,

	GEN7_3DPRIM_VERTEX_COUNT,
@@ -1072,6 +1074,8 @@ int i915_cmd_parser_get_version(void) 
	 *

	 * 1. Initial version. Checks batches and reports violations, but leaves

	 *    hardware parsing enabled (so does not allow new use cases).

	 * 2. Allow access to the MI_PREDICATE_SRC0 and

	 *    MI_PREDICATE_SRC1 registers.

	 */

	return 1;

	return 2;

}

drivers/gpu/drm/i915/i915_debugfs.c

+57 −28
Original line number Diff line number Diff line
@@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m) 
	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 rpmodectl1, rcctl1;

	u32 rpmodectl1, rcctl1, pw_status;

	unsigned fw_rendercount = 0, fw_mediacount = 0;



	intel_runtime_pm_get(dev_priv);



	pw_status = I915_READ(VLV_GTLC_PW_STATUS);

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);

	rcctl1 = I915_READ(GEN6_RC_CONTROL);
@@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m) 
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |

					GEN6_RC_CTL_EI_MODE(1))));

	seq_printf(m, "Render Power Well: %s\n",

			(I915_READ(VLV_GTLC_PW_STATUS) &

				VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");

		   (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");

	seq_printf(m, "Media Power Well: %s\n",

			(I915_READ(VLV_GTLC_PW_STATUS) &

				VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");

		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");



	seq_printf(m, "Render RC6 residency since boot: %u\n",

		   I915_READ(VLV_GT_RENDER_RC6));
@@ -1773,6 +1772,50 @@ static int i915_context_status(struct seq_file *m, void *unused) 
	return 0;

}



static void i915_dump_lrc_obj(struct seq_file *m,

			      struct intel_engine_cs *ring,

			      struct drm_i915_gem_object *ctx_obj)

{

	struct page *page;

	uint32_t *reg_state;

	int j;

	unsigned long ggtt_offset = 0;



	if (ctx_obj == NULL) {

		seq_printf(m, "Context on %s with no gem object\n",

			   ring->name);

		return;

	}



	seq_printf(m, "CONTEXT: %s %u\n", ring->name,

		   intel_execlists_ctx_id(ctx_obj));



	if (!i915_gem_obj_ggtt_bound(ctx_obj))

		seq_puts(m, "\tNot bound in GGTT\n");

	else

		ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);



	if (i915_gem_object_get_pages(ctx_obj)) {

		seq_puts(m, "\tFailed to get pages for context object\n");

		return;

	}



	page = i915_gem_object_get_page(ctx_obj, 1);

	if (!WARN_ON(page == NULL)) {

		reg_state = kmap_atomic(page);



		for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {

			seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",

				   ggtt_offset + 4096 + (j * 4),

				   reg_state[j], reg_state[j + 1],

				   reg_state[j + 2], reg_state[j + 3]);

		}

		kunmap_atomic(reg_state);

	}



	seq_putc(m, '\n');

}



static int i915_dump_lrc(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1793,29 +1836,9 @@ static int i915_dump_lrc(struct seq_file *m, void *unused) 


	list_for_each_entry(ctx, &dev_priv->context_list, link) {

		for_each_ring(ring, dev_priv, i) {

			struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;



			if (ring->default_context == ctx)

				continue;



			if (ctx_obj) {

				struct page *page = i915_gem_object_get_page(ctx_obj, 1);

				uint32_t *reg_state = kmap_atomic(page);

				int j;



				seq_printf(m, "CONTEXT: %s %u\n", ring->name,

						intel_execlists_ctx_id(ctx_obj));



				for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {

					seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",

					i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),

					reg_state[j], reg_state[j + 1],

					reg_state[j + 2], reg_state[j + 3]);

				}

				kunmap_atomic(reg_state);



				seq_putc(m, '\n');

			}

			if (ring->default_context != ctx)

				i915_dump_lrc_obj(m, ring,

						  ctx->engine[i].state);

		}

	}
@@ -1975,6 +1998,8 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
	if (IS_GEN3(dev) || IS_GEN4(dev)) {

		seq_printf(m, "DDC = 0x%08x\n",

			   I915_READ(DCC));

		seq_printf(m, "DDC2 = 0x%08x\n",

			   I915_READ(DCC2));

		seq_printf(m, "C0DRB3 = 0x%04x\n",

			   I915_READ16(C0DRB3));

		seq_printf(m, "C1DRB3 = 0x%04x\n",
@@ -1997,6 +2022,10 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",

			   I915_READ(DISP_ARB_CTL));

	}



	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)

		seq_puts(m, "L-shaped memory detected\n");



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);