Loading Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 SUBLEVEL = 90 SUBLEVEL = 91 EXTRAVERSION = NAME = "People's Front" Loading arch/arm/boot/dts/s3c6410-mini6410.dts +4 −0 Original line number Diff line number Diff line Loading @@ -165,6 +165,10 @@ }; }; &clocks { clocks = <&fin_pll>; }; &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; Loading arch/arm/boot/dts/s3c6410-smdk6410.dts +4 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,10 @@ }; }; &clocks { clocks = <&fin_pll>; }; &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; Loading arch/arm/mach-tegra/reset-handler.S +3 −3 Original line number Diff line number Diff line Loading @@ -56,16 +56,16 @@ ENTRY(tegra_resume) cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ cpu_to_csr_reg r1, r0 cpu_to_csr_reg r3, r0 mov32 r2, TEGRA_FLOW_CTRL_BASE ldr r1, [r2, r1] ldr r1, [r2, r3] /* Clear event & intr flag */ orr r1, r1, \ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps @ & ext flags for CPU power mgnt bic r1, r1, r0 str r1, [r2] str r1, [r2, r3] 1: mov32 r9, 0xc09 Loading arch/arm64/include/asm/assembler.h +5 −3 Original line number Diff line number Diff line Loading @@ -695,9 +695,11 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU .macro if_will_cond_yield_neon #ifdef CONFIG_PREEMPT get_thread_info x0 ldr x0, [x0, #TSK_TI_PREEMPT] sub x0, x0, #PREEMPT_DISABLE_OFFSET cbz x0, .Lyield_\@ ldr w1, [x0, #TSK_TI_PREEMPT] ldr x0, [x0, #TSK_TI_FLAGS] cmp w1, #PREEMPT_DISABLE_OFFSET csel x0, x0, xzr, eq tbnz x0, #TIF_NEED_RESCHED, .Lyield_\@ // needs rescheduling? /* fall through to endif_yield_neon */ .subsection 1 .Lyield_\@ : Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 SUBLEVEL = 90 SUBLEVEL = 91 EXTRAVERSION = NAME = "People's Front" Loading
arch/arm/boot/dts/s3c6410-mini6410.dts +4 −0 Original line number Diff line number Diff line Loading @@ -165,6 +165,10 @@ }; }; &clocks { clocks = <&fin_pll>; }; &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; Loading
arch/arm/boot/dts/s3c6410-smdk6410.dts +4 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,10 @@ }; }; &clocks { clocks = <&fin_pll>; }; &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; Loading
arch/arm/mach-tegra/reset-handler.S +3 −3 Original line number Diff line number Diff line Loading @@ -56,16 +56,16 @@ ENTRY(tegra_resume) cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ cpu_to_csr_reg r1, r0 cpu_to_csr_reg r3, r0 mov32 r2, TEGRA_FLOW_CTRL_BASE ldr r1, [r2, r1] ldr r1, [r2, r3] /* Clear event & intr flag */ orr r1, r1, \ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps @ & ext flags for CPU power mgnt bic r1, r1, r0 str r1, [r2] str r1, [r2, r3] 1: mov32 r9, 0xc09 Loading
arch/arm64/include/asm/assembler.h +5 −3 Original line number Diff line number Diff line Loading @@ -695,9 +695,11 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU .macro if_will_cond_yield_neon #ifdef CONFIG_PREEMPT get_thread_info x0 ldr x0, [x0, #TSK_TI_PREEMPT] sub x0, x0, #PREEMPT_DISABLE_OFFSET cbz x0, .Lyield_\@ ldr w1, [x0, #TSK_TI_PREEMPT] ldr x0, [x0, #TSK_TI_FLAGS] cmp w1, #PREEMPT_DISABLE_OFFSET csel x0, x0, xzr, eq tbnz x0, #TIF_NEED_RESCHED, .Lyield_\@ // needs rescheduling? /* fall through to endif_yield_neon */ .subsection 1 .Lyield_\@ : Loading