Merge "ARM: dts: msm: Add scalable clock for KONA"

	frequencies to limit CX peak current.

	driver in the relevant register.

- scl-clk-names:

  Usage: optional

  Value type: <string>

  Definition: Scalable clock names to identify which clocks needs to update

	along with source clock.

Example:

	qcom,vfe0@acaf000 {

		cell-index = <0>;

		clock-names-option = "ife_dsp_clk";

		clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;

		clock-rates-option = <600000000>;

		scl-clk-en;

		scl-clk-names = "ife_axi_clk";

		qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>;

		status = "ok";

	};

			<0 400000000 720000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		scl-clk-names = "ife_0_areg";

		clock-control-debugfs = "true";

		clock-names-option =  "ife_dsp_clk";

		clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;

			<0 400000000 720000000 0 0>;

		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";

		src-clock-name = "ife_clk_src";

		scl-clk-names = "ife_1_areg";

		clock-control-debugfs = "true";

		clock-names-option =  "ife_dsp_clk";

		clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;