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Commit 25660142 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux 

Pull radeon and minor nouveau fixes from Dave Airlie:
 "Just a radeon pull from Alex, fixes a few regressions since 3.7 and
  reworks some of the reset handling, and two minor nouveau fixes I
  found on the list, Ben will be back next week to take care of the
  couple of larger nouveau patches that I see outstanding."

* 'drm-next' of git://people.freedesktop.org/~airlied/linux:
  drm/nouveau: fix init with agpgart-uninorth
  drm: nouveau: Fix build warning seen if HWMON is undefined
  drm/radeon: switch to a finer grained reset for SI (v2)
  drm/radeon: switch to a finer grained reset for cayman/TN
  drm/radeon: switch to a finer grained reset for evergreen
  drm/radeon: switch to a finer grained reset for r6xx/7xx
  drm/radeon: add GPU reset flags
  drm/radeon: fix typo in evergreen dma fence
  drm/radeon: Properly handle DDC probe for DP bridges
  drm/radeon: reset dma engine on gpu reset (v2)
  drm/radeon: print dma status reg on lockup (v2)
  drm/radeon: improve ring debugfs printing
  drm/radeon: add debugfs file for dma rings
  drm/radeon/r6xx: fix DMA engine for ttm bo transfers
  drm/radeon: add connector table for Mac G4 Silver
parents 49569646 eda85d6a

drivers/gpu/drm/nouveau/nouveau_bo.c

+1 −1
Original line number Diff line number Diff line
@@ -1276,7 +1276,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 
		if (drm->agp.stat == ENABLED) {

			mem->bus.offset = mem->start << PAGE_SHIFT;

			mem->bus.base = drm->agp.base;

			mem->bus.is_iomem = true;

			mem->bus.is_iomem = !dev->agp->cant_use_aperture;

		}

#endif

		break;

drivers/gpu/drm/nouveau/nouveau_pm.c

+2 −2
Original line number Diff line number Diff line
@@ -698,10 +698,10 @@ static int 
nouveau_hwmon_init(struct drm_device *dev)

{

	struct nouveau_pm *pm = nouveau_pm(dev);

	struct nouveau_drm *drm = nouveau_drm(dev);

	struct nouveau_therm *therm = nouveau_therm(drm->device);



#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))

	struct nouveau_drm *drm = nouveau_drm(dev);

	struct nouveau_therm *therm = nouveau_therm(drm->device);

	struct device *hwmon_dev;

	int ret = 0;

drivers/gpu/drm/radeon/evergreen.c

+66 −20
Original line number Diff line number Diff line
@@ -2306,15 +2306,13 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin 
	return radeon_ring_test_lockup(rdev, ring);

}



static int evergreen_gpu_soft_reset(struct radeon_device *rdev)

static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)

{

	struct evergreen_mc_save save;

	u32 grbm_reset = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return 0;

		return;



	dev_info(rdev->dev, "GPU softreset \n");

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -2331,10 +2329,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
@@ -2358,8 +2353,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
	udelay(50);

	WREG32(GRBM_SOFT_RESET, 0);

	(void)RREG32(GRBM_SOFT_RESET);

	/* Wait a little for things to settle down */

	udelay(50);



	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -2376,13 +2370,65 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

}



static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



	/* Disable DMA */

	tmp = RREG32(DMA_RB_CNTL);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

}



static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct evergreen_mc_save save;



	if (reset_mask == 0)

		return 0;



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		evergreen_gpu_soft_reset_gfx(rdev);



	if (reset_mask & RADEON_RESET_DMA)

		evergreen_gpu_soft_reset_dma(rdev);



	/* Wait a little for things to settle down */

	udelay(50);



	evergreen_mc_resume(rdev, &save);

	return 0;

}



int evergreen_asic_reset(struct radeon_device *rdev)

{

	return evergreen_gpu_soft_reset(rdev);

	return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					       RADEON_RESET_COMPUTE |

					       RADEON_RESET_DMA));

}



/* Interrupts */
@@ -3215,7 +3261,7 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));

	/* flush HDP */

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

	radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);

	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));

	radeon_ring_write(ring, 1);

}

drivers/gpu/drm/radeon/evergreend.h

+13 −1
Original line number Diff line number Diff line
@@ -742,6 +742,7 @@ 
#define		SOFT_RESET_ROM				(1 << 14)

#define		SOFT_RESET_SEM				(1 << 15)

#define		SOFT_RESET_VMC				(1 << 17)

#define		SOFT_RESET_DMA				(1 << 20)

#define		SOFT_RESET_TST				(1 << 21)

#define		SOFT_RESET_REGBB			(1 << 22)

#define		SOFT_RESET_ORB				(1 << 23)
@@ -2027,4 +2028,15 @@ 
/* cayman packet3 addition */

#define	CAYMAN_PACKET3_DEALLOC_STATE			0x14



/* DMA regs common on r6xx/r7xx/evergreen/ni */

#define DMA_RB_CNTL                                       0xd000

#       define DMA_RB_ENABLE                              (1 << 0)

#       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */

#       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */

#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)

#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */

#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */

#define DMA_STATUS_REG                                    0xd034

#       define DMA_IDLE                                   (1 << 0)



#endif

drivers/gpu/drm/radeon/ni.c

+79 −27
Original line number Diff line number Diff line
@@ -1306,15 +1306,13 @@ void cayman_dma_fini(struct radeon_device *rdev) 
	radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);

}



static int cayman_gpu_soft_reset(struct radeon_device *rdev)

static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)

{

	struct evergreen_mc_save save;

	u32 grbm_reset = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return 0;

		return;



	dev_info(rdev->dev, "GPU softreset \n");

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -1331,19 +1329,7 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14F8));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14D8));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14FC));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14DC));



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}

	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
@@ -1368,8 +1354,6 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) 
	udelay(50);

	WREG32(GRBM_SOFT_RESET, 0);

	(void)RREG32(GRBM_SOFT_RESET);

	/* Wait a little for things to settle down */

	udelay(50);



	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));
@@ -1387,13 +1371,81 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));



}



static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



	/* dma0 */

	tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);



	/* dma1 */

	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



}



static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct evergreen_mc_save save;



	if (reset_mask == 0)

		return 0;



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14F8));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14D8));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14FC));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(0x14DC));



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		cayman_gpu_soft_reset_gfx(rdev);



	if (reset_mask & RADEON_RESET_DMA)

		cayman_gpu_soft_reset_dma(rdev);



	/* Wait a little for things to settle down */

	udelay(50);



	evergreen_mc_resume(rdev, &save);

	return 0;

}



int cayman_asic_reset(struct radeon_device *rdev)

{

	return cayman_gpu_soft_reset(rdev);

	return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					    RADEON_RESET_COMPUTE |

					    RADEON_RESET_DMA));

}



/**