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Commit 255ed515 authored by Imre Deak's avatar Imre Deak Committed by Greg Kroah-Hartman
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drm/i915/gen8+: Add RC6 CTX corruption WA 



commit 7e34f4e4aad3fd34c02b294a3cf2321adf5b4438 upstream.

In some circumstances the RC6 context can get corrupted. We can detect
this and take the required action, that is disable RC6 and runtime PM.
The HW recovers from the corrupted state after a system suspend/resume
cycle, so detect the recovery and re-enable RC6 and runtime PM.

v2: rebase (Mika)
v3:
- Move intel_suspend_gt_powersave() to the end of the GEM suspend
  sequence.
- Add commit message.
v4:
- Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API
  change.
v5: rebased on gem/gt split (Mika)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 011b7173

drivers/gpu/drm/i915/i915_drv.c

+3 −0
Original line number Diff line number Diff line
@@ -1627,6 +1627,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 
	i915_gem_suspend_late(dev_priv);



	intel_display_set_init_power(dev_priv, false);

	i915_rc6_ctx_wa_suspend(dev_priv);

	intel_uncore_suspend(dev_priv);



	/*
@@ -1853,6 +1854,8 @@ static int i915_drm_resume_early(struct drm_device *dev) 
	else

		intel_display_set_init_power(dev_priv, true);



	i915_rc6_ctx_wa_resume(dev_priv);



	intel_engines_sanitize(dev_priv);



	enable_rpm_wakeref_asserts(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+5 −2
Original line number Diff line number Diff line
@@ -801,6 +801,7 @@ struct intel_rps { 


struct intel_rc6 {

	bool enabled;

	bool ctx_corrupted;

	u64 prev_hw_residency[4];

	u64 cur_residency[4];

};
@@ -2557,10 +2558,12 @@ intel_info(const struct drm_i915_private *dev_priv) 
/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))



#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\

	(IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) == 9)



/* WaRsDisableCoarsePowerGating:skl,cnl */

#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \

	(IS_CANNONLAKE(dev_priv) || \

	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))

	(IS_CANNONLAKE(dev_priv) || INTEL_GEN(dev_priv) == 9)



#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)

#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \

drivers/gpu/drm/i915/i915_gem.c

+8 −0
Original line number Diff line number Diff line
@@ -174,6 +174,11 @@ static u32 __i915_gem_park(struct drm_i915_private *i915) 
	if (INTEL_GEN(i915) >= 6)

		gen6_rps_idle(i915);



	if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) {

		i915_rc6_ctx_wa_check(i915);

		intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);

	}



	intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);



	intel_runtime_pm_put(i915);
@@ -220,6 +225,9 @@ void i915_gem_unpark(struct drm_i915_private *i915) 
	 */

	intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);



	if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))

		intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);



	i915->gt.awake = true;

	if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */

		i915->gt.epoch = 1;

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -387,6 +387,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)



#define GEN8_RC6_CTX_INFO		_MMIO(0x8504)



#define GAC_ECO_BITS			_MMIO(0x14090)

#define   ECOBITS_SNB_BIT		(1 << 13)

#define   ECOBITS_PPGTT_CACHE64B	(3 << 8)

drivers/gpu/drm/i915/intel_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -2064,6 +2064,9 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv); 
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);

void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);

void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);

bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);

void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);

void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);

void gen6_rps_busy(struct drm_i915_private *dev_priv);

void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);

void gen6_rps_idle(struct drm_i915_private *dev_priv);