Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25518a1e authored by David Dai's avatar David Dai Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: Add bw voting ops for clk-alpha-pll and rcg 



Add callbacks to vote for bandwidth for the sake of accessing
multimedia clock controllers to clock operators.

Change-Id: I4b911deadaa9d8fd5a79b9b0bf68fa38e7172719
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 8f643002

drivers/clk/qcom/clk-alpha-pll.c

+14 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#include "clk-alpha-pll.h"

#include "common.h"

#include "clk-debug.h"



#define PLL_MODE(p)		((p)->offset + 0x0)

# define PLL_OUTCTRL		BIT(0)
@@ -1109,6 +1110,7 @@ const struct clk_ops clk_alpha_pll_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
@@ -1119,6 +1121,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { 
	.recalc_rate = alpha_pll_huayra_recalc_rate,

	.round_rate = alpha_pll_huayra_round_rate,

	.set_rate = alpha_pll_huayra_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
@@ -1130,6 +1133,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_alpha_pll_hwfsm_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -1141,6 +1145,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_zonda_pll_set_rate,

	.list_registers = clk_zonda_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
@@ -1233,12 +1238,14 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = { 
	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_round_rate,

	.set_rate = clk_alpha_pll_postdiv_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);



const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {

	.round_rate = clk_alpha_pll_postdiv_round_ro_rate,

	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
@@ -1407,6 +1414,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops = { 
	.set_rate = alpha_pll_fabia_set_rate,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
@@ -1416,6 +1424,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 
	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
@@ -1501,6 +1510,7 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 
	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
@@ -1508,6 +1518,7 @@ const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = { 
	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
@@ -1869,6 +1880,7 @@ const struct clk_ops clk_alpha_pll_lucid_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_set_rate,

	.list_registers = clk_alpha_pll_lucid_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
@@ -1879,6 +1891,7 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_alpha_pll_lucid_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
@@ -1886,5 +1899,6 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 
	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);

drivers/clk/qcom/clk-branch.c

+5 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2013, 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2017-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -179,6 +179,7 @@ const struct clk_ops clk_branch_ops = { 
	.disable = clk_branch_disable,

	.is_enabled = clk_is_enabled_regmap,

	.set_flags = clk_branch_set_flags,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch_ops);
@@ -368,6 +369,7 @@ const struct clk_ops clk_branch2_ops = { 
	.set_flags = clk_branch_set_flags,

	.list_registers = clk_branch2_list_registers,

	.debug_init = clk_debug_measure_add,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch2_ops);
@@ -433,6 +435,7 @@ const struct clk_ops clk_branch2_hw_ctl_ops = { 
	.recalc_rate = clk_branch2_hw_ctl_recalc_rate,

	.determine_rate = clk_branch2_hw_ctl_determine_rate,

	.set_flags = clk_branch_set_flags,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch2_hw_ctl_ops);
@@ -440,5 +443,6 @@ const struct clk_ops clk_branch_simple_ops = { 
	.enable = clk_enable_regmap,

	.disable = clk_disable_regmap,

	.is_enabled = clk_is_enabled_regmap,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_branch_simple_ops);

drivers/clk/qcom/clk-debug.c

+6 −0
Original line number Diff line number Diff line
@@ -381,3 +381,9 @@ int clk_debug_measure_register(struct clk_hw *hw) 
}

EXPORT_SYMBOL(clk_debug_measure_register);



void clk_debug_bus_vote(struct clk_hw *hw, bool enable)

{

	if (hw->init->bus_cl_id)

		msm_bus_scale_client_update_request(hw->init->bus_cl_id,

								enable);

}

drivers/clk/qcom/clk-debug.h

+1 −0
Original line number Diff line number Diff line
@@ -130,5 +130,6 @@ extern const struct clk_ops clk_debug_mux_ops; 


int clk_debug_measure_register(struct clk_hw *hw);

void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);

void clk_debug_bus_vote(struct clk_hw *hw, bool enable);



#endif

drivers/clk/qcom/clk-rcg2.c

+11 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 


#include "clk-rcg.h"

#include "common.h"

#include "clk-debug.h"



#define CMD_REG			0x0

#define CMD_UPDATE		BIT(0)
@@ -703,6 +704,7 @@ const struct clk_ops clk_rcg2_ops = { 
	.set_rate_and_parent = clk_rcg2_set_rate_and_parent,

	.list_rate = clk_rcg2_list_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_ops);
@@ -716,6 +718,7 @@ const struct clk_ops clk_rcg2_floor_ops = { 
	.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,

	.list_rate = clk_rcg2_list_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
@@ -846,6 +849,7 @@ const struct clk_ops clk_edp_pixel_ops = { 
	.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,

	.determine_rate = clk_edp_pixel_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
@@ -907,6 +911,7 @@ const struct clk_ops clk_byte_ops = { 
	.set_rate_and_parent = clk_byte_set_rate_and_parent,

	.determine_rate = clk_byte_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_byte_ops);
@@ -978,6 +983,7 @@ const struct clk_ops clk_byte2_ops = { 
	.set_rate_and_parent = clk_byte2_set_rate_and_parent,

	.determine_rate = clk_byte2_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_byte2_ops);
@@ -1069,6 +1075,7 @@ const struct clk_ops clk_pixel_ops = { 
	.set_rate_and_parent = clk_pixel_set_rate_and_parent,

	.determine_rate = clk_pixel_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_pixel_ops);
@@ -1152,6 +1159,7 @@ const struct clk_ops clk_dp_ops = { 
	.set_rate_and_parent = clk_dp_set_rate_and_parent,

	.determine_rate = clk_dp_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_dp_ops);
@@ -1247,6 +1255,7 @@ const struct clk_ops clk_gfx3d_ops = { 
	.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,

	.determine_rate = clk_gfx3d_determine_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
@@ -1359,6 +1368,7 @@ const struct clk_ops clk_rcg2_shared_ops = { 
	.set_rate = clk_rcg2_shared_set_rate,

	.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
@@ -1655,5 +1665,6 @@ const struct clk_ops clk_rcg2_dependent_ops = { 
	.set_rate_and_parent = clk_rcg2_dependent_set_rate_and_parent,

	.list_rate = clk_rcg2_list_rate,

	.list_registers = clk_rcg2_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL(clk_rcg2_dependent_ops);