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Commit 25499d93 authored by Anand Gadiyar's avatar Anand Gadiyar Committed by Paul Walmsley
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OMAP3: wait on IDLEST after enabling USBTLL fclk 



We need to wait on the IDLEST bit after the clocks are enabled
before attempting to access any register.

Currently, the USBTLL i-clock ops uses the clkops_omap2_dflt_wait,
while the USBTLL f-clock ops uses clkops_omap2_dflt. If the
i-clock is enabled first, the clkops_omap2_dflt_wait is
short-circuited as the companion f-clock is not enabled.
This can cause a data abort if the IDLEST has not transitioned,
and we try to access a USBTLL register.

Since the USBTLL i-clock and f-clock could be enabled in any order,
this is a bug. Fix it by changing the clkops for the f-clock.

Signed-off-by: default avatarAnand Gadiyar <gadiyar@ti.com>
Acked-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent b37fa16e

arch/arm/mach-omap2/clock3xxx_data.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1408,7 +1408,7 @@ static struct clk ts_fck = { 




static struct clk usbtll_fck = {

static struct clk usbtll_fck = {

	.name		= "usbtll_fck",

	.name		= "usbtll_fck",

	.ops		= &clkops_omap2_dflt,

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll5_m2_ck,

	.parent		= &dpll5_m2_ck,

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),

	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,

	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,