Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25451c19 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

some misc radeon fixes.

* 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/amdgpu: fix irq domain remove for tonga ih
  drm/radeon: use helper for mst connector dpms.
  drm/radeon/mst: port some MST setup code from DAL.
  drm/amdgpu: add invisible pin size statistic
parents 92881524 303f551c
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -2034,6 +2034,7 @@ struct amdgpu_device {

	/* tracking pinned memory */
	u64 vram_pin_size;
	u64 invisible_pin_size;
	u64 gart_pin_size;

	/* amdkfd interface */
+1 −1
Original line number Diff line number Diff line
@@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
		vram_gtt.vram_size = adev->mc.real_vram_size;
		vram_gtt.vram_size -= adev->vram_pin_size;
		vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
		vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
		vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
		vram_gtt.gtt_size  = adev->mc.gtt_size;
		vram_gtt.gtt_size -= adev->gart_pin_size;
		return copy_to_user(out, &vram_gtt,
+8 −4
Original line number Diff line number Diff line
@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = amdgpu_bo_gpu_offset(bo);
		if (domain == AMDGPU_GEM_DOMAIN_VRAM)
		if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
			bo->adev->vram_pin_size += amdgpu_bo_size(bo);
		else
			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
				bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
		} else
			bo->adev->gart_pin_size += amdgpu_bo_size(bo);
	} else {
		dev_err(bo->adev->dev, "%p pin failed\n", bo);
@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
	}
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (likely(r == 0)) {
		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
		if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
		else
			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
				bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
		} else
			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
	} else {
		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);
	amdgpu_irq_add_domain(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}
+2 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@
#define NI_DP_MSE_SAT2                                 0x7398

#define NI_DP_MSE_SAT_UPDATE                           0x739c
#       define NI_DP_MSE_SAT_UPDATE_MASK               0x3
#       define NI_DP_MSE_16_MTP_KEEPOUT                0x100

#define NI_DIG_BE_CNTL                                 0x7140
#       define NI_DIG_FE_SOURCE_SELECT(x)              (((x) & 0x7f) << 8)
Loading