Commit 24cf8467 authored Aug 16, 2016 by Stephane Eranian Committed by Ingo Molnar Sep 05, 2016

perf/x86/intel/uncore: Handle non-standard counter offset



The offset of the counters for UPI and M2M boxes on Skylake server is
non-standard (8 bytes apart).

This patch introduces a custom flag UNCORE_BOX_FLAG_CTL_OFFS8 to
specially handle it.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1471378190-17276-2-git-send-email-kan.liang@intel.com


Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent 68ce4a0d

arch/x86/events/intel/uncore.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -120,6 +120,7 @@ struct intel_uncore_box {
		};

		#define UNCORE_BOX_FLAG_INITIATED 0
		#define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte apart */

		struct uncore_event_desc {
		struct kobj_attribute attr;
		@@ -172,6 +173,9 @@ static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
		static inline
		unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
		{
		if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
		return idx * 8 + box->pmu->type->event_ctl;

		return idx * 4 + box->pmu->type->event_ctl;
		}