Loading asoc/codecs/bolero/rx-macro.c +7 −2 Original line number Diff line number Diff line Loading @@ -1623,6 +1623,9 @@ static int rx_macro_config_classh(struct snd_soc_component *component, 0x40, 0x40); break; case INTERP_AUX: snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x08, 0x08); snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x10, 0x10); Loading Loading @@ -2197,16 +2200,18 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component, (interp_idx * RX_MACRO_RX_PATH_OFFSET); dsm_reg = BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL + (interp_idx * RX_MACRO_RX_PATH_OFFSET); if (interp_idx == INTERP_AUX) dsm_reg = BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL; rx_cfg2_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG2 + (interp_idx * RX_MACRO_RX_PATH_OFFSET); if (SND_SOC_DAPM_EVENT_ON(event)) { if (rx_priv->main_clk_users[interp_idx] == 0) { snd_soc_component_update_bits(component, dsm_reg, 0x01, 0x01); /* Main path PGA mute enable */ snd_soc_component_update_bits(component, main_reg, 0x10, 0x10); snd_soc_component_update_bits(component, dsm_reg, 0x01, 0x01); /* Clk enable */ snd_soc_component_update_bits(component, main_reg, 0x20, 0x20); Loading asoc/sm8250-port-config.h +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0}, {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, }; Loading Loading
asoc/codecs/bolero/rx-macro.c +7 −2 Original line number Diff line number Diff line Loading @@ -1623,6 +1623,9 @@ static int rx_macro_config_classh(struct snd_soc_component *component, 0x40, 0x40); break; case INTERP_AUX: snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x08, 0x08); snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x10, 0x10); Loading Loading @@ -2197,16 +2200,18 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component, (interp_idx * RX_MACRO_RX_PATH_OFFSET); dsm_reg = BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL + (interp_idx * RX_MACRO_RX_PATH_OFFSET); if (interp_idx == INTERP_AUX) dsm_reg = BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL; rx_cfg2_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG2 + (interp_idx * RX_MACRO_RX_PATH_OFFSET); if (SND_SOC_DAPM_EVENT_ON(event)) { if (rx_priv->main_clk_users[interp_idx] == 0) { snd_soc_component_update_bits(component, dsm_reg, 0x01, 0x01); /* Main path PGA mute enable */ snd_soc_component_update_bits(component, main_reg, 0x10, 0x10); snd_soc_component_update_bits(component, dsm_reg, 0x01, 0x01); /* Clk enable */ snd_soc_component_update_bits(component, main_reg, 0x20, 0x20); Loading
asoc/sm8250-port-config.h +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0}, {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, }; Loading