Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 22fc6ecc authored by Ravikiran G Thirumalai's avatar Ravikiran G Thirumalai Committed by Linus Torvalds
Browse files

[PATCH] Change maxaligned_in_smp alignemnt macros to internodealigned_in_smp macros 



____cacheline_maxaligned_in_smp is currently used to align critical structures
and avoid false sharing.  It uses per-arch L1_CACHE_SHIFT_MAX and people find
L1_CACHE_SHIFT_MAX useless.

However, we have been using ____cacheline_maxaligned_in_smp to align
structures on the internode cacheline size.  As per Andi's suggestion,
following patch kills ____cacheline_maxaligned_in_smp and introduces
INTERNODE_CACHE_SHIFT, which defaults to L1_CACHE_SHIFT for all arches.
Arches needing L3/Internode cacheline alignment can define
INTERNODE_CACHE_SHIFT in the arch asm/cache.h.  Patch replaces
____cacheline_maxaligned_in_smp with ____cacheline_internodealigned_in_smp

With this patch, L1_CACHE_SHIFT_MAX can be killed

Signed-off-by: default avatarRavikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: default avatarShai Fultheim <shai@scalex86.org>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 6d524aed

arch/i386/kernel/init_task.c

+1 −1
Original line number Diff line number Diff line
@@ -42,5 +42,5 @@ EXPORT_SYMBOL(init_task); 
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,

 * no more per-task TSS's.

 */ 

DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;

DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;

arch/i386/kernel/irq.c

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#include <linux/cpu.h>

#include <linux/delay.h>



DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_maxaligned_in_smp;

DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;

EXPORT_PER_CPU_SYMBOL(irq_stat);



#ifndef CONFIG_X86_LOCAL_APIC

arch/x86_64/kernel/init_task.c

+1 −1
Original line number Diff line number Diff line
@@ -44,6 +44,6 @@ EXPORT_SYMBOL(init_task); 
 * section. Since TSS's are completely CPU-local, we want them

 * on exact cacheline boundaries, to eliminate cacheline ping-pong.

 */ 

DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;

DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;



#define ALIGN_TO_4K __attribute__((section(".data.init_task")))

include/linux/cache.h

+13 −4
Original line number Diff line number Diff line
@@ -45,12 +45,21 @@ 
#endif /* CONFIG_SMP */

#endif



#if !defined(____cacheline_maxaligned_in_smp)

/*

 * The maximum alignment needed for some critical structures

 * These could be inter-node cacheline sizes/L3 cacheline

 * size etc.  Define this in asm/cache.h for your arch

 */

#ifndef INTERNODE_CACHE_SHIFT

#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT

#endif



#if !defined(____cacheline_internodealigned_in_smp)

#if defined(CONFIG_SMP)

#define ____cacheline_maxaligned_in_smp \

	__attribute__((__aligned__(1 << (L1_CACHE_SHIFT_MAX))))

#define ____cacheline_internodealigned_in_smp \

	__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))

#else

#define ____cacheline_maxaligned_in_smp

#define ____cacheline_internodealigned_in_smp

#endif

#endif

include/linux/ide.h

+1 −1
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ typedef struct hwif_s { 
	unsigned dma;



	void (*led_act)(void *data, int rw);

} ____cacheline_maxaligned_in_smp ide_hwif_t;

} ____cacheline_internodealigned_in_smp ide_hwif_t;



/*

 *  internal ide interrupt handler type