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Commit 22b19086 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] nommu: provide a way for correct control register value selection 



Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 264edb35

arch/arm/mm/proc-arm1020.S

+7 −9
Original line number Diff line number Diff line
@@ -440,11 +440,12 @@ __arm1020_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif



	adr	r5, arm1020_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1020_cr1_clear

	bic	r0, r0, r5

	ldr	r5, arm1020_cr1_set

	orr	r0, r0, r5

	orr	r0, r0, r6

#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN

	orr	r0, r0, #0x4000 		@ .R.. .... .... ....

#endif
@@ -456,12 +457,9 @@ __arm1020_setup: 
	 * .RVI ZFRS BLDP WCAM

	 * .011 1001 ..11 0101

	 */

	.type	arm1020_cr1_clear, #object

	.type	arm1020_cr1_set, #object

arm1020_cr1_clear:

	.word	0x593f

arm1020_cr1_set:

	.word	0x3935

	.type	arm1020_crval, #object

arm1020_crval:

	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930



	__INITDATA

arch/arm/mm/proc-arm1020e.S

+6 −9
Original line number Diff line number Diff line
@@ -422,11 +422,11 @@ __arm1020e_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif

	adr	r5, arm1020e_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1020e_cr1_clear

	bic	r0, r0, r5

	ldr	r5, arm1020e_cr1_set

	orr	r0, r0, r5

	orr	r0, r0, r6

#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN

	orr	r0, r0, #0x4000 		@ .R.. .... .... ....

#endif
@@ -438,12 +438,9 @@ __arm1020e_setup: 
	 * .RVI ZFRS BLDP WCAM

	 * .011 1001 ..11 0101

	 */

	.type	arm1020e_cr1_clear, #object

	.type	arm1020e_cr1_set, #object

arm1020e_cr1_clear:

	.word	0x5f3f

arm1020e_cr1_set:

	.word	0x3935

	.type	arm1020e_crval, #object

arm1020e_crval:

	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930



	__INITDATA

arch/arm/mm/proc-arm1022.S

+6 −9
Original line number Diff line number Diff line
@@ -404,11 +404,11 @@ __arm1022_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4

#endif

	adr	r5, arm1022_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1022_cr1_clear

	bic	r0, r0, r5

	ldr	r5, arm1022_cr1_set

	orr	r0, r0, r5

	orr	r0, r0, r6

#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN

	orr	r0, r0, #0x4000 		@ .R..............

#endif
@@ -421,12 +421,9 @@ __arm1022_setup: 
	 * .011 1001 ..11 0101

	 * 

	 */

	.type	arm1022_cr1_clear, #object

	.type	arm1022_cr1_set, #object

arm1022_cr1_clear:

	.word	0x7f3f

arm1022_cr1_set:

	.word	0x3935

	.type	arm1022_crval, #object

arm1022_crval:

	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930



	__INITDATA

arch/arm/mm/proc-arm1026.S

+6 −9
Original line number Diff line number Diff line
@@ -399,11 +399,11 @@ __arm1026_setup: 
	mov	r0, #4				@ explicitly disable writeback

	mcr	p15, 7, r0, c15, c0, 0

#endif

	adr	r5, arm1026_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register v4

	ldr	r5, arm1026_cr1_clear

	bic	r0, r0, r5

	ldr	r5, arm1026_cr1_set

	orr	r0, r0, r5

	orr	r0, r0, r6

#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN

	orr	r0, r0, #0x4000 		@ .R.. .... .... ....

#endif
@@ -416,12 +416,9 @@ __arm1026_setup: 
	 * .011 1001 ..11 0101

	 * 

	 */

	.type	arm1026_cr1_clear, #object

	.type	arm1026_cr1_set, #object

arm1026_cr1_clear:

	.word	0x7f3f

arm1026_cr1_set:

	.word	0x3935

	.type	arm1026_crval, #object

arm1026_crval:

	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934



	__INITDATA

arch/arm/mm/proc-arm720.S

+6 −9
Original line number Diff line number Diff line
@@ -169,11 +169,11 @@ __arm720_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)

#endif

	adr	r5, arm720_crval

	ldmia	r5, {r5, r6}

	mrc	p15, 0, r0, c1, c0		@ get control register

	ldr	r5, arm720_cr1_clear

	bic	r0, r0, r5

	ldr	r5, arm720_cr1_set

	orr	r0, r0, r5

	orr	r0, r0, r6

	mov	pc, lr				@ __ret (head.S)

	.size	__arm720_setup, . - __arm720_setup
@@ -183,12 +183,9 @@ __arm720_setup: 
	 * ..1. 1001 ..11 1101

	 * 

	 */

	.type	arm720_cr1_clear, #object

	.type	arm720_cr1_set, #object

arm720_cr1_clear:

	.word	0x2f3f

arm720_cr1_set:

	.word	0x213d

	.type	arm720_crval, #object

arm720_crval:

	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130



		__INITDATA