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Commit 227318bb authored by Anton Blanchard's avatar Anton Blanchard Committed by Paul Mackerras
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[POWERPC] Remove stale 64bit on 32bit kernel code



Remove some stale POWER3/POWER4/970 on 32bit kernel support.

Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 8555a002
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+0 −1
Original line number Original line Diff line number Diff line
@@ -108,7 +108,6 @@ ifeq ($(CONFIG_6xx),y)
CFLAGS		+= -mcpu=powerpc
CFLAGS		+= -mcpu=powerpc
endif
endif


cpu-as-$(CONFIG_PPC64BRIDGE)	+= -Wa,-mppc64bridge
cpu-as-$(CONFIG_4xx)		+= -Wa,-m405
cpu-as-$(CONFIG_4xx)		+= -Wa,-m405
cpu-as-$(CONFIG_6xx)		+= -Wa,-maltivec
cpu-as-$(CONFIG_6xx)		+= -Wa,-maltivec
cpu-as-$(CONFIG_POWER4)		+= -Wa,-maltivec
cpu-as-$(CONFIG_POWER4)		+= -Wa,-maltivec
+0 −8
Original line number Original line Diff line number Diff line
@@ -189,17 +189,11 @@ struct cpu_spec cpu_specs[] = {
		.oprofile_type		= PPC_OPROFILE_POWER4,
		.oprofile_type		= PPC_OPROFILE_POWER4,
		.platform		= "ppc970",
		.platform		= "ppc970",
	},
	},
#endif /* CONFIG_PPC64 */
#if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
	{	/* PPC970FX */
	{	/* PPC970FX */
		.pvr_mask		= 0xffff0000,
		.pvr_mask		= 0xffff0000,
		.pvr_value		= 0x003c0000,
		.pvr_value		= 0x003c0000,
		.cpu_name		= "PPC970FX",
		.cpu_name		= "PPC970FX",
#ifdef CONFIG_PPC32
		.cpu_features		= CPU_FTRS_970_32,
#else
		.cpu_features		= CPU_FTRS_PPC970,
		.cpu_features		= CPU_FTRS_PPC970,
#endif
		.cpu_user_features	= COMMON_USER_POWER4 |
		.cpu_user_features	= COMMON_USER_POWER4 |
			PPC_FEATURE_HAS_ALTIVEC_COMP,
			PPC_FEATURE_HAS_ALTIVEC_COMP,
		.icache_bsize		= 128,
		.icache_bsize		= 128,
@@ -210,8 +204,6 @@ struct cpu_spec cpu_specs[] = {
		.oprofile_type		= PPC_OPROFILE_POWER4,
		.oprofile_type		= PPC_OPROFILE_POWER4,
		.platform		= "ppc970",
		.platform		= "ppc970",
	},
	},
#endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
#ifdef CONFIG_PPC64
	{	/* PPC970MP */
	{	/* PPC970MP */
		.pvr_mask		= 0xffff0000,
		.pvr_mask		= 0xffff0000,
		.pvr_value		= 0x00440000,
		.pvr_value		= 0x00440000,
+0 −34
Original line number Original line Diff line number Diff line
@@ -74,12 +74,6 @@ _GLOBAL(hash_page_sync)
 */
 */
	.text
	.text
_GLOBAL(hash_page)
_GLOBAL(hash_page)
#ifdef CONFIG_PPC64BRIDGE
	mfmsr	r0
	clrldi	r0,r0,1		/* make sure it's in 32-bit mode */
	MTMSRD(r0)
	isync
#endif
	tophys(r7,0)			/* gets -KERNELBASE into r7 */
	tophys(r7,0)			/* gets -KERNELBASE into r7 */
#ifdef CONFIG_SMP
#ifdef CONFIG_SMP
	addis	r8,r7,mmu_hash_lock@h
	addis	r8,r7,mmu_hash_lock@h
@@ -285,7 +279,6 @@ Hash_base = 0xc0180000
Hash_bits = 12				/* e.g. 256kB hash table */
Hash_bits = 12				/* e.g. 256kB hash table */
Hash_msk = (((1 << Hash_bits) - 1) * 64)
Hash_msk = (((1 << Hash_bits) - 1) * 64)


#ifndef CONFIG_PPC64BRIDGE
/* defines for the PTE format for 32-bit PPCs */
/* defines for the PTE format for 32-bit PPCs */
#define PTE_SIZE	8
#define PTE_SIZE	8
#define PTEG_SIZE	64
#define PTEG_SIZE	64
@@ -299,21 +292,6 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64)
#define SET_V(r)	oris r,r,PTE_V@h
#define SET_V(r)	oris r,r,PTE_V@h
#define CLR_V(r,t)	rlwinm r,r,0,1,31
#define CLR_V(r,t)	rlwinm r,r,0,1,31


#else
/* defines for the PTE format for 64-bit PPCs */
#define PTE_SIZE	16
#define PTEG_SIZE	128
#define LG_PTEG_SIZE	7
#define LDPTEu		ldu
#define STPTE		std
#define CMPPTE		cmpd
#define PTE_H		2
#define PTE_V		1
#define TST_V(r)	andi. r,r,PTE_V
#define SET_V(r)	ori r,r,PTE_V
#define CLR_V(r,t)	li t,PTE_V; andc r,r,t
#endif /* CONFIG_PPC64BRIDGE */

#define HASH_LEFT	31-(LG_PTEG_SIZE+Hash_bits-1)
#define HASH_LEFT	31-(LG_PTEG_SIZE+Hash_bits-1)
#define HASH_RIGHT	31-LG_PTEG_SIZE
#define HASH_RIGHT	31-LG_PTEG_SIZE


@@ -331,14 +309,8 @@ BEGIN_FTR_SECTION
END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)


	/* Construct the high word of the PPC-style PTE (r5) */
	/* Construct the high word of the PPC-style PTE (r5) */
#ifndef CONFIG_PPC64BRIDGE
	rlwinm	r5,r3,7,1,24		/* put VSID in 0x7fffff80 bits */
	rlwinm	r5,r3,7,1,24		/* put VSID in 0x7fffff80 bits */
	rlwimi	r5,r4,10,26,31		/* put in API (abbrev page index) */
	rlwimi	r5,r4,10,26,31		/* put in API (abbrev page index) */
#else /* CONFIG_PPC64BRIDGE */
	clrlwi	r3,r3,8			/* reduce vsid to 24 bits */
	sldi	r5,r3,12		/* shift vsid into position */
	rlwimi	r5,r4,16,20,24		/* put in API (abbrev page index) */
#endif /* CONFIG_PPC64BRIDGE */
	SET_V(r5)			/* set V (valid) bit */
	SET_V(r5)			/* set V (valid) bit */


	/* Get the address of the primary PTE group in the hash table (r3) */
	/* Get the address of the primary PTE group in the hash table (r3) */
@@ -516,14 +488,8 @@ _GLOBAL(flush_hash_pages)
	add	r3,r3,r0		/* note code below trims to 24 bits */
	add	r3,r3,r0		/* note code below trims to 24 bits */


	/* Construct the high word of the PPC-style PTE (r11) */
	/* Construct the high word of the PPC-style PTE (r11) */
#ifndef CONFIG_PPC64BRIDGE
	rlwinm	r11,r3,7,1,24		/* put VSID in 0x7fffff80 bits */
	rlwinm	r11,r3,7,1,24		/* put VSID in 0x7fffff80 bits */
	rlwimi	r11,r4,10,26,31		/* put in API (abbrev page index) */
	rlwimi	r11,r4,10,26,31		/* put in API (abbrev page index) */
#else /* CONFIG_PPC64BRIDGE */
	clrlwi	r3,r3,8			/* reduce vsid to 24 bits */
	sldi	r11,r3,12		/* shift vsid into position */
	rlwimi	r11,r4,16,20,24		/* put in API (abbrev page index) */
#endif /* CONFIG_PPC64BRIDGE */
	SET_V(r11)			/* set V (valid) bit */
	SET_V(r11)			/* set V (valid) bit */


#ifdef CONFIG_SMP
#ifdef CONFIG_SMP
+0 −10
Original line number Original line Diff line number Diff line
@@ -42,11 +42,7 @@ unsigned long _SDR1;


union ubat {			/* BAT register values to be loaded */
union ubat {			/* BAT register values to be loaded */
	BAT	bat;
	BAT	bat;
#ifdef CONFIG_PPC64BRIDGE
	u64	word[2];
#else
	u32	word[2];
	u32	word[2];
#endif
} BATS[4][2];			/* 4 pairs of IBAT, DBAT */
} BATS[4][2];			/* 4 pairs of IBAT, DBAT */


struct batrange {		/* stores address ranges mapped by BATs */
struct batrange {		/* stores address ranges mapped by BATs */
@@ -220,15 +216,9 @@ void __init MMU_init_hw(void)


	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);


#ifdef CONFIG_PPC64BRIDGE
#define LG_HPTEG_SIZE	7		/* 128 bytes per HPTEG */
#define SDR1_LOW_BITS	(lg_n_hpteg - 11)
#define MIN_N_HPTEG	2048		/* min 256kB hash table */
#else
#define LG_HPTEG_SIZE	6		/* 64 bytes per HPTEG */
#define LG_HPTEG_SIZE	6		/* 64 bytes per HPTEG */
#define SDR1_LOW_BITS	((n_hpteg - 1) >> 10)
#define SDR1_LOW_BITS	((n_hpteg - 1) >> 10)
#define MIN_N_HPTEG	1024		/* min 64kB hash table */
#define MIN_N_HPTEG	1024		/* min 64kB hash table */
#endif


	/*
	/*
	 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
	 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
+1 −5
Original line number Original line Diff line number Diff line
@@ -23,14 +23,10 @@
#define CACHE_LINE_SIZE		16
#define CACHE_LINE_SIZE		16
#define LG_CACHE_LINE_SIZE	4
#define LG_CACHE_LINE_SIZE	4
#define MAX_COPY_PREFETCH	1
#define MAX_COPY_PREFETCH	1
#elif !defined(CONFIG_PPC64BRIDGE)
#else
#define CACHE_LINE_SIZE		32
#define CACHE_LINE_SIZE		32
#define LG_CACHE_LINE_SIZE	5
#define LG_CACHE_LINE_SIZE	5
#define MAX_COPY_PREFETCH	4
#define MAX_COPY_PREFETCH	4
#else
#define CACHE_LINE_SIZE		128
#define LG_CACHE_LINE_SIZE	7
#define MAX_COPY_PREFETCH	1
#endif /* CONFIG_4xx || CONFIG_8xx */
#endif /* CONFIG_4xx || CONFIG_8xx */


	.text
	.text
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