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Commit 223437c7 authored Mar 30, 2015 by Kaixu Xia Committed by Greg Kroah-Hartman Apr 03, 2015

coresight: remove the unnecessary configuration coresight-default-sink



The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.

Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent a0a500ef

Documentation/devicetree/bindings/arm/coresight.txt

+0 −1

Original line number	Diff line number	Diff line
		@@ -61,7 +61,6 @@ Example:
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		coresight-default-sink;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {

arch/arm/boot/dts/hip04.dtsi

+0 −1

Original line number	Diff line number	Diff line
		@@ -275,7 +275,6 @@
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0xe3c42000 0 0x1000>;

		coresight-default-sink;
		clocks = <&clk_375m>;
		clock-names = "apb_pclk";
		port {

arch/arm/boot/dts/omap3-beagle-xm.dts

+0 −1

Original line number	Diff line number	Diff line
		@@ -150,7 +150,6 @@
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0x5401b000 0x1000>;

		coresight-default-sink;
		clocks = <&emu_src_ck>;
		clock-names = "apb_pclk";
		port {

arch/arm/boot/dts/omap3-beagle.dts

+0 −1

Original line number	Diff line number	Diff line
		@@ -145,7 +145,6 @@
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0x5401b000 0x1000>;

		coresight-default-sink;
		clocks = <&emu_src_ck>;
		clock-names = "apb_pclk";
		port {

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

+0 −1

Original line number	Diff line number	Diff line
		@@ -362,7 +362,6 @@
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		coresight-default-sink;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		port {