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Commit 21e438af authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: update cik_tiling_mode_table_init() for hawaii 



Hawaii uses a different tiling configuration.  Add support
for it.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 939c0d3c

drivers/gpu/drm/radeon/cik.c

+220 −2
Original line number Diff line number Diff line
@@ -1758,9 +1758,227 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 


	num_pipe_configs = rdev->config.cik.max_tile_pipes;

	if (num_pipe_configs > 8)

		num_pipe_configs = 8; /* ??? */

		num_pipe_configs = 16;



	if (num_pipe_configs == 8) {

	if (num_pipe_configs == 16) {

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {

			switch (reg_offset) {

			case 0:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));

				break;

			case 1:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));

				break;

			case 2:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));

				break;

			case 3:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));

				break;

			case 4:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(split_equal_to_row_size));

				break;

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

			case 6:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));

				break;

			case 7:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 TILE_SPLIT(split_equal_to_row_size));

				break;

			case 8:

				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));

				break;

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

				break;

			case 10:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 11:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 12:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

			case 14:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 16:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 17:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

				break;

			case 28:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 29:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			case 30:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));

				break;

			default:

				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {

			switch (reg_offset) {

			case 0:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 1:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 2:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 3:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 4:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_8_BANK));

				break;

			case 5:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_4_BANK));

				break;

			case 6:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_2_BANK));

				break;

			case 8:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 9:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 10:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_16_BANK));

				break;

			case 11:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_8_BANK));

				break;

			case 12:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_4_BANK));

				break;

			case 13:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_2_BANK));

				break;

			case 14:

				gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |

						 NUM_BANKS(ADDR_SURF_2_BANK));

				break;

			default:

				gb_tile_moden = 0;

				break;

			}

			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else if (num_pipe_configs == 8) {

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {

			switch (reg_offset) {

			case 0:

drivers/gpu/drm/radeon/cikd.h

+2 −0
Original line number Diff line number Diff line
@@ -1164,6 +1164,8 @@ 
#              define	ADDR_SURF_P8_32x32_16x16		12

#              define	ADDR_SURF_P8_32x32_16x32		13

#              define	ADDR_SURF_P8_32x64_32x32		14

#              define	ADDR_SURF_P16_32x32_8x16		16

#              define	ADDR_SURF_P16_32x32_16x16		17

#       define TILE_SPLIT(x)					((x) << 11)

#              define	ADDR_SURF_TILE_SPLIT_64B		0

#              define	ADDR_SURF_TILE_SPLIT_128B		1