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Commit 21bdbb71 authored by Neil Leeder's avatar Neil Leeder Committed by Will Deacon
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perf: add qcom l2 cache perf events driver 



Adds perf events support for L2 cache PMU.

The L2 cache PMU driver is named 'l2cache_0' and can be used
with perf events to profile L2 events such as cache hits
and misses on Qualcomm Technologies processors.

Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarNeil Leeder <nleeder@codeaurora.org>
[will: minimise nesting in l2_cache_associate_cpu_with_cluster]
[will: use kstrtoul for unsigned long, remove redunant .owner setting]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent fe0a7ef7

Documentation/perf/qcom_l2_pmu.txt

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Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)

=====================================================================



This driver supports the L2 cache clusters found in Qualcomm Technologies

Centriq SoCs. There are multiple physical L2 cache clusters, each with their

own PMU. Each cluster has one or more CPUs associated with it.



There is one logical L2 PMU exposed, which aggregates the results from

the physical PMUs.



The driver provides a description of its available events and configuration

options in sysfs, see /sys/devices/l2cache_0.



The "format" directory describes the format of the events.



Events can be envisioned as a 2-dimensional array. Each column represents

a group of events. There are 8 groups. Only one entry from each

group can be in use at a time. If multiple events from the same group

are specified, the conflicting events cannot be counted at the same time.



Events are specified as 0xCCG, where CC is 2 hex digits specifying

the code (array row) and G specifies the group (column) 0-7.



In addition there is a cycle counter event specified by the value 0xFE

which is outside the above scheme.



The driver provides a "cpumask" sysfs attribute which contains a mask

consisting of one CPU per cluster which will be used to handle all the PMU

events on that cluster.



Examples for use with perf:



  perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1



  perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1



The driver does not support sampling, therefore "perf record" will

not work. Per-task perf sessions are not supported.

drivers/perf/Kconfig

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@@ -12,6 +12,15 @@ config ARM_PMU 
	  Say y if you want to use CPU performance monitors on ARM-based

	  systems.



config QCOM_L2_PMU

	bool "Qualcomm Technologies L2-cache PMU"

	depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI

	  help

	  Provides support for the L2 cache performance monitor unit (PMU)

	  in Qualcomm Technologies processors.

	  Adds the L2 cache PMU into the perf events subsystem for

	  monitoring L2 cache events.



config XGENE_PMU

        depends on PERF_EVENTS && ARCH_XGENE

        bool "APM X-Gene SoC PMU"

drivers/perf/Makefile

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obj-$(CONFIG_ARM_PMU) += arm_pmu.o

obj-$(CONFIG_QCOM_L2_PMU)	+= qcom_l2_pmu.o

obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o

drivers/perf/qcom_l2_pmu.c

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File added.

Preview size limit exceeded, changes collapsed.

include/linux/cpuhotplug.h

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@@ -138,6 +138,7 @@ enum cpuhp_state { 
	CPUHP_AP_PERF_ARM_CCI_ONLINE,

	CPUHP_AP_PERF_ARM_CCN_ONLINE,

	CPUHP_AP_PERF_ARM_L2X0_ONLINE,

	CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,

	CPUHP_AP_WORKQUEUE_ONLINE,

	CPUHP_AP_RCUTREE_ONLINE,

	CPUHP_AP_ONLINE_DYN,