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Commit 218b6fd1 authored by Neeraj Upadhyay's avatar Neeraj Upadhyay
Browse files

drivers: llcc: Do not do cacheable mode settings for v1 



For LLCC hardware version 1, cache override registers are
expected to be static one time configured by firmware and
HLOS might not even have access to these override registers.
So, remove the configuration from LLCC driver.

Change-Id: I39468de00d54ba7fc82f8cfcdaae9e98c7bd30ac
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent db92782e

drivers/soc/qcom/llcc-slice.c

+0 −12
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ 


#define LLCC_TRP_C_AS_NC	      0x21F90

#define LLCC_TRP_NC_AS_C	      0x21F94

#define LLCC_FEAC_C_AS_NC	      0x35030

#define LLCC_FEAC_NC_AS_C	      0x35034

#define LLCC_TRP_WRSC_EN              0x21F20

#define LLCC_WRSC_SCID_EN(n)          BIT(n)
@@ -262,16 +260,6 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) 
						 LLCC_TRP_NC_AS_C, mask);

		if (ret)

			return ret;

	} else {

		ret  = regmap_write(drv_data->bcast_regmap,

						 LLCC_FEAC_C_AS_NC, 0);

		if (ret)

			return ret;



		ret = regmap_write(drv_data->bcast_regmap,

						 LLCC_FEAC_NC_AS_C, mask);

		if (ret)

			return ret;

	}



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