Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 217c6d21 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx',... 

Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx', 'pci/host-exynos', 'pci/host-hisi', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-qcom' and 'pci/host-spear' into next

* pci/host-armada:
  MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver
  PCI: armada: Reorder struct armada8k_pcie
  PCI: armada: Pass device-specific struct to internal functions
  PCI: armada: Use generic DesignWare accessors
  PCI: armada: Remove redundant struct armada8k_pcie.base
  PCI: armada: Add local base pointer
  PCI: armada: Remove unused platform data

* pci/host-artpec:
  PCI: artpec6: Add resource name comments
  PCI: artpec6: Pass device-specific struct to internal functions
  PCI: artpec6: Remove unnecessary artpec6_pcie_link_up()
  PCI: artpec6: Use generic DesignWare accessors
  PCI: artpec6: Add register accessors
  PCI: artpec6: Remove unused platform data
  PCI: artpec6: Add local struct device pointers

* pci/host-dra7xx:
  PCI: dra7xx: Reorder struct dra7xx_pcie
  PCI: dra7xx: Move struct pcie_port setup to probe function
  PCI: dra7xx: Pass device-specific struct to internal functions
  PCI: dra7xx: Use generic DesignWare accessors
  PCI: dra7xx: Set drvdata at end of probe function
  PCI: dra7xx: Remove redundant struct device pointer from dra7xx_pcie
  PCI: dra7xx: Add local struct device pointers

* pci/host-exynos:
  PCI: exynos: Reorder struct exynos_pcie
  PCI: exynos: Pass device-specific struct to internal functions
  PCI: exynos: Name private struct pointer "exynos_pcie" consistently
  PCI: exynos: Uninline register accessors
  PCI: exynos: Add local struct device pointers

* pci/host-hisi:
  PCI: hisi: Reorder struct hisi_pcie
  PCI: hisi: Pass device-specific struct to internal functions
  PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
  PCI: hisi: Use generic DesignWare accessors
  PCI: hisi: Remove redundant struct hisi_pcie.reg_base
  PCI: hisi: Name private struct pointer "hisi_pcie" consistently
  PCI: hisi: Remove unused platform data
  PCI: hisi: Add local struct device pointers

* pci/host-imx6:
  PCI: imx6: Remove unused return values
  PCI: imx6: Reorder struct imx6_pcie
  PCI: imx6: Use generic DesignWare accessors
  PCI: imx6: Pass device-specific struct to internal functions
  PCI: imx6: Pass struct imx6_pcie to PHY accessors
  PCI: imx6: Removed unused struct imx6_pcie.mem_base
  PCI: imx6: Remove redundant of_node pointer
  PCI: imx6: Add local struct device pointers

* pci/host-keystone:
  PCI: keystone: Reorder struct keystone_pcie
  PCI: keystone: Add app register accessors
  PCI: keystone: Pass keystone_pcie, not va_app_base, to DBI functions
  PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
  PCI: keystone: Use generic DesignWare accessors
  PCI: keystone: Add local struct device pointers

* pci/host-layerscape:
  PCI: layerscape: Reorder struct ls_pcie
  PCI: layerscape: Remove unused ls_add_pcie_port() platform_device arg
  PCI: layerscape: Move struct pcie_port setup to probe function
  PCI: layerscape: Pass device-specific struct to internal functions
  PCI: layerscape: Remove redundant struct ls_pcie.dbi
  PCI: layerscape: Remove unused platform data
  PCI: layerscape: Add local struct device pointers

* pci/host-qcom:
  PCI: qcom: Reorder struct qcom_pcie
  PCI: qcom: Remove redundant struct qcom_pcie.dev
  PCI: qcom: Remove redundant struct qcom_pcie.dbi
  PCI: qcom: Remove unused platform data

* pci/host-spear:
  PCI: spear: Clean up struct device usage
  PCI: spear: Reorder struct spear13xx_pcie
  PCI: spear: Pass device-specific struct to internal functions
  PCI: spear: Remove unused constants
parents 22c7e1d4 3dc9d38c 7c62efcf 8e5ec414 6b1f185a f84cfdf7 9ab021b6 4841f3ad 6caaa28d ee053694 6a43a425

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -8936,6 +8936,14 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/versatile.txt

F:	drivers/pci/host/pci-versatile.c



PCI DRIVER FOR ARMADA 8K

M:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

L:	linux-pci@vger.kernel.org

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/pci-armada8k.txt

F:	drivers/pci/host/pcie-armada8k.c



PCI DRIVER FOR APPLIEDMICRO XGENE

M:	Tanmay Inamdar <tinamdar@apm.com>

L:	linux-pci@vger.kernel.org

drivers/pci/host/pci-dra7xx.c

+45 −58
Original line number Diff line number Diff line
@@ -64,11 +64,10 @@ 
#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF



struct dra7xx_pcie {

	void __iomem		*base;

	struct phy		**phy;

	int			phy_count;

	struct device		*dev;

	struct pcie_port	pp;

	void __iomem		*base;		/* DT ti_conf */

	int			phy_count;	/* DT phy-names count */

	struct phy		**phy;

};



#define to_dra7xx_pcie(x)	container_of((x), struct dra7xx_pcie, pp)
@@ -84,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, 
	writel(value, pcie->base + offset);

}



static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)

{

	return readl(pp->dbi_base + offset);

}



static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,

					 u32 value)

{

	writel(value, pp->dbi_base + offset);

}



static int dra7xx_pcie_link_up(struct pcie_port *pp)

{

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
@@ -103,13 +91,14 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp) 
	return !!(reg & LINK_UP);

}



static int dra7xx_pcie_establish_link(struct pcie_port *pp)

static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)

{

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

	struct pcie_port *pp = &dra7xx->pp;

	struct device *dev = pp->dev;

	u32 reg;



	if (dw_pcie_link_up(pp)) {

		dev_err(pp->dev, "link is already up\n");

		dev_err(dev, "link is already up\n");

		return 0;

	}
@@ -120,10 +109,8 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp) 
	return dw_pcie_wait_for_link(pp);

}



static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)

static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)

{

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);



	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,

			   ~INTERRUPTS);

	dra7xx_pcie_writel(dra7xx,
@@ -142,6 +129,8 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) 


static void dra7xx_pcie_host_init(struct pcie_port *pp)

{

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);



	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;

	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;

	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
@@ -149,10 +138,10 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) 


	dw_pcie_setup_rc(pp);



	dra7xx_pcie_establish_link(pp);

	dra7xx_pcie_establish_link(dra7xx);

	if (IS_ENABLED(CONFIG_PCI_MSI))

		dw_pcie_msi_init(pp);

	dra7xx_pcie_enable_interrupts(pp);

	dra7xx_pcie_enable_interrupts(dra7xx);

}



static struct pcie_host_ops dra7xx_pcie_host_ops = {
@@ -196,8 +185,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) 


static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)

{

	struct pcie_port *pp = arg;

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

	struct dra7xx_pcie *dra7xx = arg;

	struct pcie_port *pp = &dra7xx->pp;

	u32 reg;



	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
@@ -223,51 +212,51 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) 
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)

{

	struct dra7xx_pcie *dra7xx = arg;

	struct device *dev = dra7xx->pp.dev;

	u32 reg;



	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);



	if (reg & ERR_SYS)

		dev_dbg(dra7xx->dev, "System Error\n");

		dev_dbg(dev, "System Error\n");



	if (reg & ERR_FATAL)

		dev_dbg(dra7xx->dev, "Fatal Error\n");

		dev_dbg(dev, "Fatal Error\n");



	if (reg & ERR_NONFATAL)

		dev_dbg(dra7xx->dev, "Non Fatal Error\n");

		dev_dbg(dev, "Non Fatal Error\n");



	if (reg & ERR_COR)

		dev_dbg(dra7xx->dev, "Correctable Error\n");

		dev_dbg(dev, "Correctable Error\n");



	if (reg & ERR_AXI)

		dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");

		dev_dbg(dev, "AXI tag lookup fatal Error\n");



	if (reg & ERR_ECRC)

		dev_dbg(dra7xx->dev, "ECRC Error\n");

		dev_dbg(dev, "ECRC Error\n");



	if (reg & PME_TURN_OFF)

		dev_dbg(dra7xx->dev,

		dev_dbg(dev,

			"Power Management Event Turn-Off message received\n");



	if (reg & PME_TO_ACK)

		dev_dbg(dra7xx->dev,

		dev_dbg(dev,

			"Power Management Turn-Off Ack message received\n");



	if (reg & PM_PME)

		dev_dbg(dra7xx->dev,

			"PM Power Management Event message received\n");

		dev_dbg(dev, "PM Power Management Event message received\n");



	if (reg & LINK_REQ_RST)

		dev_dbg(dra7xx->dev, "Link Request Reset\n");

		dev_dbg(dev, "Link Request Reset\n");



	if (reg & LINK_UP_EVT)

		dev_dbg(dra7xx->dev, "Link-up state change\n");

		dev_dbg(dev, "Link-up state change\n");



	if (reg & CFG_BME_EVT)

		dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");

		dev_dbg(dev, "CFG 'Bus Master Enable' change\n");



	if (reg & CFG_MSE_EVT)

		dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");

		dev_dbg(dev, "CFG 'Memory Space Enable' change\n");



	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
@@ -278,13 +267,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 
				       struct platform_device *pdev)

{

	int ret;

	struct pcie_port *pp;

	struct pcie_port *pp = &dra7xx->pp;

	struct device *dev = pp->dev;

	struct resource *res;

	struct device *dev = &pdev->dev;



	pp = &dra7xx->pp;

	pp->dev = dev;

	pp->ops = &dra7xx_pcie_host_ops;



	pp->irq = platform_get_irq(pdev, 1);

	if (pp->irq < 0) {
@@ -292,12 +277,11 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 
		return -EINVAL;

	}



	ret = devm_request_irq(&pdev->dev, pp->irq,

			       dra7xx_pcie_msi_irq_handler,

	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,

			       IRQF_SHARED | IRQF_NO_THREAD,

			       "dra7-pcie-msi",	pp);

			       "dra7-pcie-msi",	dra7xx);

	if (ret) {

		dev_err(&pdev->dev, "failed to request irq\n");

		dev_err(dev, "failed to request irq\n");

		return ret;

	}
@@ -314,7 +298,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 


	ret = dw_pcie_host_init(pp);

	if (ret) {

		dev_err(dra7xx->dev, "failed to initialize host\n");

		dev_err(dev, "failed to initialize host\n");

		return ret;

	}
@@ -332,6 +316,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
	void __iomem *base;

	struct resource *res;

	struct dra7xx_pcie *dra7xx;

	struct pcie_port *pp;

	struct device *dev = &pdev->dev;

	struct device_node *np = dev->of_node;

	char name[10];
@@ -343,6 +328,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
	if (!dra7xx)

		return -ENOMEM;



	pp = &dra7xx->pp;

	pp->dev = dev;

	pp->ops = &dra7xx_pcie_host_ops;



	irq = platform_get_irq(pdev, 0);

	if (irq < 0) {

		dev_err(dev, "missing IRQ resource\n");
@@ -390,7 +379,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 


	dra7xx->base = base;

	dra7xx->phy = phy;

	dra7xx->dev = dev;

	dra7xx->phy_count = phy_count;



	pm_runtime_enable(dev);
@@ -407,7 +395,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
		ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,

					    "pcie_reset");

		if (ret) {

			dev_err(&pdev->dev, "gpio%d request failed, ret %d\n",

			dev_err(dev, "gpio%d request failed, ret %d\n",

				gpio_sel, ret);

			goto err_gpio;

		}
@@ -420,12 +408,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
	reg &= ~LTSSM_EN;

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);



	platform_set_drvdata(pdev, dra7xx);



	ret = dra7xx_add_pcie_port(dra7xx, pdev);

	if (ret < 0)

		goto err_gpio;



	platform_set_drvdata(pdev, dra7xx);

	return 0;



err_gpio:
@@ -451,9 +438,9 @@ static int dra7xx_pcie_suspend(struct device *dev) 
	u32 val;



	/* clear MSE */

	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);

	val = dw_pcie_readl_rc(pp, PCI_COMMAND);

	val &= ~PCI_COMMAND_MEMORY;

	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);

	dw_pcie_writel_rc(pp, PCI_COMMAND, val);



	return 0;

}
@@ -465,9 +452,9 @@ static int dra7xx_pcie_resume(struct device *dev) 
	u32 val;



	/* set MSE */

	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);

	val = dw_pcie_readl_rc(pp, PCI_COMMAND);

	val |= PCI_COMMAND_MEMORY;

	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);

	dw_pcie_writel_rc(pp, PCI_COMMAND, val);



	return 0;

}

drivers/pci/host/pci-exynos.c

+100 −114
Original line number Diff line number Diff line
@@ -29,13 +29,13 @@ 
#define to_exynos_pcie(x)	container_of(x, struct exynos_pcie, pp)



struct exynos_pcie {

	void __iomem		*elbi_base;

	void __iomem		*phy_base;

	void __iomem		*block_base;

	struct pcie_port	pp;

	void __iomem		*elbi_base;	/* DT 0th resource */

	void __iomem		*phy_base;	/* DT 1st resource */

	void __iomem		*block_base;	/* DT 2nd resource */

	int			reset_gpio;

	struct clk		*clk;

	struct clk		*bus_clk;

	struct pcie_port	pp;

};



/* PCIe ELBI registers */
@@ -102,40 +102,40 @@ struct exynos_pcie { 
#define PCIE_PHY_TRSV3_PD_TSV		(0x1 << 7)

#define PCIE_PHY_TRSV3_LVCC		0x31c



static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)

static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)

{

	writel(val, pcie->elbi_base + reg);

	writel(val, exynos_pcie->elbi_base + reg);

}



static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)

static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)

{

	return readl(pcie->elbi_base + reg);

	return readl(exynos_pcie->elbi_base + reg);

}



static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)

static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)

{

	writel(val, pcie->phy_base + reg);

	writel(val, exynos_pcie->phy_base + reg);

}



static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)

static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)

{

	return readl(pcie->phy_base + reg);

	return readl(exynos_pcie->phy_base + reg);

}



static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)

static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)

{

	writel(val, pcie->block_base + reg);

	writel(val, exynos_pcie->block_base + reg);

}



static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)

static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)

{

	return readl(pcie->block_base + reg);

	return readl(exynos_pcie->block_base + reg);

}



static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)

static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,

					    bool on)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	if (on) {

		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
@@ -148,10 +148,10 @@ static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) 
	}

}



static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)

static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos_pcie,

					    bool on)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	if (on) {

		val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
@@ -164,10 +164,9 @@ static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on) 
	}

}



static void exynos_pcie_assert_core_reset(struct pcie_port *pp)

static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);

	val &= ~PCIE_CORE_RESET_ENABLE;
@@ -177,10 +176,9 @@ static void exynos_pcie_assert_core_reset(struct pcie_port *pp) 
	exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);

}



static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)

static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);

	val |= PCIE_CORE_RESET_ENABLE;
@@ -193,18 +191,14 @@ static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) 
	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);

}



static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)

static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos_pcie)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);

	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);

}



static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)

static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos_pcie)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);

	exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);

	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
@@ -213,10 +207,9 @@ static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) 
	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);

}



static void exynos_pcie_power_on_phy(struct pcie_port *pp)

static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);

	val &= ~PCIE_PHY_COMMON_PD_CMN;
@@ -239,10 +232,9 @@ static void exynos_pcie_power_on_phy(struct pcie_port *pp) 
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);

}



static void exynos_pcie_power_off_phy(struct pcie_port *pp)

static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);

	val |= PCIE_PHY_COMMON_PD_CMN;
@@ -265,10 +257,8 @@ static void exynos_pcie_power_off_phy(struct pcie_port *pp) 
	exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);

}



static void exynos_pcie_init_phy(struct pcie_port *pp)

static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	/* DCC feedback control off */

	exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
@@ -305,51 +295,41 @@ static void exynos_pcie_init_phy(struct pcie_port *pp) 
	exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);

}



static void exynos_pcie_assert_reset(struct pcie_port *pp)

static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	struct pcie_port *pp = &exynos_pcie->pp;

	struct device *dev = pp->dev;



	if (exynos_pcie->reset_gpio >= 0)

		devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,

		devm_gpio_request_one(dev, exynos_pcie->reset_gpio,

				GPIOF_OUT_INIT_HIGH, "RESET");

}



static int exynos_pcie_establish_link(struct pcie_port *pp)

static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	struct pcie_port *pp = &exynos_pcie->pp;

	struct device *dev = pp->dev;

	u32 val;



	if (dw_pcie_link_up(pp)) {

		dev_err(pp->dev, "Link already up\n");

		dev_err(dev, "Link already up\n");

		return 0;

	}



	/* assert reset signals */

	exynos_pcie_assert_core_reset(pp);

	exynos_pcie_assert_phy_reset(pp);



	/* de-assert phy reset */

	exynos_pcie_deassert_phy_reset(pp);



	/* power on phy */

	exynos_pcie_power_on_phy(pp);



	/* initialize phy */

	exynos_pcie_init_phy(pp);

	exynos_pcie_assert_core_reset(exynos_pcie);

	exynos_pcie_assert_phy_reset(exynos_pcie);

	exynos_pcie_deassert_phy_reset(exynos_pcie);

	exynos_pcie_power_on_phy(exynos_pcie);

	exynos_pcie_init_phy(exynos_pcie);



	/* pulse for common reset */

	exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);

	udelay(500);

	exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);



	/* de-assert core reset */

	exynos_pcie_deassert_core_reset(pp);



	/* setup root complex */

	exynos_pcie_deassert_core_reset(exynos_pcie);

	dw_pcie_setup_rc(pp);



	/* assert reset signal */

	exynos_pcie_assert_reset(pp);

	exynos_pcie_assert_reset(exynos_pcie);



	/* assert LTSSM enable */

	exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
@@ -361,27 +341,23 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) 


	while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {

		val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);

		dev_info(pp->dev, "PLL Locked: 0x%x\n", val);

		dev_info(dev, "PLL Locked: 0x%x\n", val);

	}

	/* power off phy */

	exynos_pcie_power_off_phy(pp);



	exynos_pcie_power_off_phy(exynos_pcie);

	return -ETIMEDOUT;

}



static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)

static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);

	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);

}



static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)

static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos_pcie)

{

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	/* enable INTX interrupt */

	val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
@@ -391,23 +367,24 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) 


static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)

{

	struct pcie_port *pp = arg;

	struct exynos_pcie *exynos_pcie = arg;



	exynos_pcie_clear_irq_pulse(pp);

	exynos_pcie_clear_irq_pulse(exynos_pcie);

	return IRQ_HANDLED;

}



static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)

{

	struct pcie_port *pp = arg;

	struct exynos_pcie *exynos_pcie = arg;

	struct pcie_port *pp = &exynos_pcie->pp;



	return dw_handle_msi_irq(pp);

}



static void exynos_pcie_msi_init(struct pcie_port *pp)

static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie)

{

	struct pcie_port *pp = &exynos_pcie->pp;

	u32 val;

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	dw_pcie_msi_init(pp);
@@ -417,58 +394,64 @@ static void exynos_pcie_msi_init(struct pcie_port *pp) 
	exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);

}



static void exynos_pcie_enable_interrupts(struct pcie_port *pp)

static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)

{

	exynos_pcie_enable_irq_pulse(pp);

	exynos_pcie_enable_irq_pulse(exynos_pcie);



	if (IS_ENABLED(CONFIG_PCI_MSI))

		exynos_pcie_msi_init(pp);

		exynos_pcie_msi_init(exynos_pcie);

}



static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)

static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	u32 val;



	exynos_pcie_sideband_dbi_r_mode(pp, true);

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);

	val = readl(pp->dbi_base + reg);

	exynos_pcie_sideband_dbi_r_mode(pp, false);

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);

	return val;

}



static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)

static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)

{

	exynos_pcie_sideband_dbi_w_mode(pp, true);

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);

	writel(val, pp->dbi_base + reg);

	exynos_pcie_sideband_dbi_w_mode(pp, false);

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);

}



static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,

				u32 *val)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	int ret;



	exynos_pcie_sideband_dbi_r_mode(pp, true);

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);

	ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_r_mode(pp, false);

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);

	return ret;

}



static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,

				u32 val)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	int ret;



	exynos_pcie_sideband_dbi_w_mode(pp, true);

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);

	ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_w_mode(pp, false);

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);

	return ret;

}



static int exynos_pcie_link_up(struct pcie_port *pp)

{

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

	u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);

	u32 val;



	val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);

	if (val == PCIE_ELBI_LTSSM_ENABLE)

		return 1;
@@ -477,8 +460,10 @@ static int exynos_pcie_link_up(struct pcie_port *pp) 


static void exynos_pcie_host_init(struct pcie_port *pp)

{

	exynos_pcie_establish_link(pp);

	exynos_pcie_enable_interrupts(pp);

	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);



	exynos_pcie_establish_link(exynos_pcie);

	exynos_pcie_enable_interrupts(exynos_pcie);

}



static struct pcie_host_ops exynos_pcie_host_ops = {
@@ -490,36 +475,38 @@ static struct pcie_host_ops exynos_pcie_host_ops = { 
	.host_init = exynos_pcie_host_init,

};



static int __init exynos_add_pcie_port(struct pcie_port *pp,

static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,

				       struct platform_device *pdev)

{

	struct pcie_port *pp = &exynos_pcie->pp;

	struct device *dev = pp->dev;

	int ret;



	pp->irq = platform_get_irq(pdev, 1);

	if (!pp->irq) {

		dev_err(&pdev->dev, "failed to get irq\n");

		dev_err(dev, "failed to get irq\n");

		return -ENODEV;

	}

	ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,

				IRQF_SHARED, "exynos-pcie", pp);

	ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,

				IRQF_SHARED, "exynos-pcie", exynos_pcie);

	if (ret) {

		dev_err(&pdev->dev, "failed to request irq\n");

		dev_err(dev, "failed to request irq\n");

		return ret;

	}



	if (IS_ENABLED(CONFIG_PCI_MSI)) {

		pp->msi_irq = platform_get_irq(pdev, 0);

		if (!pp->msi_irq) {

			dev_err(&pdev->dev, "failed to get msi irq\n");

			dev_err(dev, "failed to get msi irq\n");

			return -ENODEV;

		}



		ret = devm_request_irq(&pdev->dev, pp->msi_irq,

		ret = devm_request_irq(dev, pp->msi_irq,

					exynos_pcie_msi_irq_handler,

					IRQF_SHARED | IRQF_NO_THREAD,

					"exynos-pcie", pp);

					"exynos-pcie", exynos_pcie);

		if (ret) {

			dev_err(&pdev->dev, "failed to request msi irq\n");

			dev_err(dev, "failed to request msi irq\n");

			return ret;

		}

	}
@@ -529,7 +516,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp, 


	ret = dw_pcie_host_init(pp);

	if (ret) {

		dev_err(&pdev->dev, "failed to initialize host\n");

		dev_err(dev, "failed to initialize host\n");

		return ret;

	}
@@ -538,37 +525,36 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp, 


static int __init exynos_pcie_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct exynos_pcie *exynos_pcie;

	struct pcie_port *pp;

	struct device_node *np = pdev->dev.of_node;

	struct device_node *np = dev->of_node;

	struct resource *elbi_base;

	struct resource *phy_base;

	struct resource *block_base;

	int ret;



	exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),

				GFP_KERNEL);

	exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);

	if (!exynos_pcie)

		return -ENOMEM;



	pp = &exynos_pcie->pp;



	pp->dev = &pdev->dev;

	pp->dev = dev;



	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);



	exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");

	exynos_pcie->clk = devm_clk_get(dev, "pcie");

	if (IS_ERR(exynos_pcie->clk)) {

		dev_err(&pdev->dev, "Failed to get pcie rc clock\n");

		dev_err(dev, "Failed to get pcie rc clock\n");

		return PTR_ERR(exynos_pcie->clk);

	}

	ret = clk_prepare_enable(exynos_pcie->clk);

	if (ret)

		return ret;



	exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");

	exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");

	if (IS_ERR(exynos_pcie->bus_clk)) {

		dev_err(&pdev->dev, "Failed to get pcie bus clock\n");

		dev_err(dev, "Failed to get pcie bus clock\n");

		ret = PTR_ERR(exynos_pcie->bus_clk);

		goto fail_clk;

	}
@@ -577,27 +563,27 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) 
		goto fail_clk;



	elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);

	exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base);

	if (IS_ERR(exynos_pcie->elbi_base)) {

		ret = PTR_ERR(exynos_pcie->elbi_base);

		goto fail_bus_clk;

	}



	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);

	exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);

	exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base);

	if (IS_ERR(exynos_pcie->phy_base)) {

		ret = PTR_ERR(exynos_pcie->phy_base);

		goto fail_bus_clk;

	}



	block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);

	exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);

	exynos_pcie->block_base = devm_ioremap_resource(dev, block_base);

	if (IS_ERR(exynos_pcie->block_base)) {

		ret = PTR_ERR(exynos_pcie->block_base);

		goto fail_bus_clk;

	}



	ret = exynos_add_pcie_port(pp, pdev);

	ret = exynos_add_pcie_port(exynos_pcie, pdev);

	if (ret < 0)

		goto fail_bus_clk;

drivers/pci/host/pci-imx6.c

+126 −124

File changed.

Preview size limit exceeded, changes collapsed.

drivers/pci/host/pci-keystone-dw.c

+69 −54

File changed.

Preview size limit exceeded, changes collapsed.