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Commit 2123f442 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Use cdclk_state->voltage on BXT/GLK 



Track the system agent voltage we request from pcode in the cdclk state
on BXT/GLK. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.

v2: s/voltage/voltage_level/ (Rodrigo)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-7-ville.syrjala@linux.intel.com
parent 2aa97491

drivers/gpu/drm/i915/intel_cdclk.c

+21 −2
Original line number Diff line number Diff line
@@ -1163,6 +1163,11 @@ static int glk_calc_cdclk(int min_cdclk) 
		return 79200;

}



static u8 bxt_calc_voltage_level(int cdclk)

{

	return DIV_ROUND_UP(cdclk, 25000);

}



static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)

{

	int ratio;
@@ -1239,7 +1244,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
	cdclk_state->cdclk = cdclk_state->ref;



	if (cdclk_state->vco == 0)

		return;

		goto out;



	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
@@ -1263,6 +1268,14 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
	}



	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);



 out:

	/*

	 * Can't read this out :( Let's assume it's

	 * at least what the CDCLK frequency requires.

	 */

	cdclk_state->voltage_level =

		bxt_calc_voltage_level(cdclk_state->cdclk);

}



static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1365,7 +1378,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 


	mutex_lock(&dev_priv->pcu_lock);

	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,

				      DIV_ROUND_UP(cdclk, 25000));

				      cdclk_state->voltage_level);

	mutex_unlock(&dev_priv->pcu_lock);



	if (ret) {
@@ -1457,6 +1470,7 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv) 
		cdclk_state.cdclk = bxt_calc_cdclk(0);

		cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);

	}

	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);



	bxt_set_cdclk(dev_priv, &cdclk_state);

}
@@ -1474,6 +1488,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) 


	cdclk_state.cdclk = cdclk_state.ref;

	cdclk_state.vco = 0;

	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);



	bxt_set_cdclk(dev_priv, &cdclk_state);

}
@@ -2031,6 +2046,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) 


	intel_state->cdclk.logical.vco = vco;

	intel_state->cdclk.logical.cdclk = cdclk;

	intel_state->cdclk.logical.voltage_level =

		bxt_calc_voltage_level(cdclk);



	if (!intel_state->active_crtcs) {

		if (IS_GEMINILAKE(dev_priv)) {
@@ -2043,6 +2060,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) 


		intel_state->cdclk.actual.vco = vco;

		intel_state->cdclk.actual.cdclk = cdclk;

		intel_state->cdclk.actual.voltage_level =

			bxt_calc_voltage_level(cdclk);

	} else {

		intel_state->cdclk.actual =

			intel_state->cdclk.logical;