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Commit 20cad1e5 authored by Visweswara Tanuku's avatar Visweswara Tanuku
Browse files

ARM: dts: msm: Add 4-wire UART SE0 dt nodes for DIAG 

Added QUPv3 device tree entries for 4-wire UART
over SE0 in scuba platform for DIAG over UART.

Change-Id: I1bff4a4e987435986c59752bd385b6717a4bd604
parent f622e6dd

qcom/scuba-pinctrl.dtsi

+69 −0
Original line number Diff line number Diff line
@@ -324,6 +324,75 @@ 
			};

		};



		qupv3_se0_4uart_pins: qupv3_se0_4uart_pins {

			qupv3_se0_default_ctsrtsrx:

				qupv3_se0_default_ctsrtsrx {

				mux {

					pins = "gpio0", "gpio1", "gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1", "gpio3";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se0_default_tx:

				qupv3_se0_default_tx {

				mux {

					pins = "gpio2";

					function = "gpio";

				};



				config {

					pins = "gpio2";

					drive-strength = <2>;

					bias-pull-up;

				};

			};



			qupv3_se0_ctsrx: qupv3_se0_ctsrx {

				mux {

					pins = "gpio0", "gpio3";

					function = "qup0";

				};



				config {

					pins = "gpio0", "gpio3";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se0_rts: qupv3_se0_rts {

				mux {

					pins = "gpio1";

					function = "qup0";

				};



				config {

					pins = "gpio1";

					drive-strength = <2>;

					bias-pull-down;

				};

			};



			qupv3_se0_tx: qupv3_se0_tx {

				mux {

					pins = "gpio2";

					function = "qup0";

				};



				config {

					pins = "gpio2";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {

			qupv3_se1_i2c_active: qupv3_se1_i2c_active {

				mux {

qcom/scuba-qupv3.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -108,6 +108,25 @@ 
		status = "disabled";

	};



	/* 4-wire UART Instance for DIAG */

	qupv3_se0_4uart: qcom,qup_uart@4a80000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x4a80000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>,

				<&qupv3_se0_tx>;

		pinctrl-1 = <&qupv3_se0_default_ctsrtsrx>,

				<&qupv3_se0_default_tx>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se1_i2c: i2c@4a84000 {

		compatible = "qcom,i2c-geni";

		reg = <0x4a84000 0x4000>;