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Commit 20a85cc2 authored by Tatenda Chipeperekwa's avatar Tatenda Chipeperekwa
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clk: qcom: mdss: update the PHY programming for DisplayPort 



Update the PHY programming for DisplayPort so that it matches the
latest published hardware programming guide.

Change-Id: I8ea67a511649d3b00f93ea6da449a70c1d3c8ecb
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent 08c90a00

drivers/clk/qcom/mdss/mdss-dp-pll-7nm-util.c

+3 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define DP_PHY_PD_CTL				0x0018

#define DP_PHY_MODE				0x001C



#define DP_PHY_AUX_CFG1				0x0024

#define DP_PHY_AUX_CFG2				0x0028



#define DP_PHY_VCO_DIV				0x0070
@@ -405,7 +406,8 @@ static int dp_pll_enable_7nm(struct clk_hw *hw) 
	struct dp_pll_db_7nm *pdb = (struct dp_pll_db_7nm *)dp_res->priv;

	u32 bias_en, drvr_en;



	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_AUX_CFG2, 0x24);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_AUX_CFG1, 0x13);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_AUX_CFG2, 0xA4);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x05);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);