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Commit 1fdd783e authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/glk: Calculate high/low switch count for GLK 



As per BSPEC, high/low switch count to be programmed in
terms of byteclock using exit_zero_count and prep_count.
For Geminilake exit/prep counts are already calculated
in terms of byteclock. This patch calculates high/low
switch count using counts value in byteclock, old calculation
leads to screen flicker/shift issue while resuming from S3/S4.

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1494336565-19185-1-git-send-email-madhav.chauhan@intel.com
parent 9081d080

drivers/gpu/drm/i915/intel_dsi_vbt.c

+4 −4
Original line number Diff line number Diff line
@@ -694,8 +694,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 
						clk_zero_cnt << 8 | prepare_cnt;



	/*

	 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2

	 *					+ 10UI + Extra Byte Count

	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *

	 *					mul + 10UI + Extra Byte Count

	 *

	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count

	 * Extra Byte Count is calculated according to number of lanes.
@@ -708,8 +708,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 
	/* B044 */

	/* FIXME:

	 * The comment above does not match with the code */

	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +

						exit_zero_cnt * 2 + 10, 8);

	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +

						exit_zero_cnt * mul + 10, 8);



	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);