Loading drivers/iommu/arm-smmu.c +9 −10 Original line number Diff line number Diff line Loading @@ -1526,20 +1526,19 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); } static int arm_smmu_domain_has_cap(struct iommu_domain *domain, unsigned long cap) static bool arm_smmu_capable(enum iommu_cap cap) { struct arm_smmu_domain *smmu_domain = domain->priv; struct arm_smmu_device *smmu = smmu_domain->smmu; u32 features = smmu ? smmu->features : 0; switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return features & ARM_SMMU_FEAT_COHERENT_WALK; /* * Return true here as the SMMU can always send out coherent * requests. */ return true; case IOMMU_CAP_INTR_REMAP: return 1; /* MSIs are just memory writes */ return true; /* MSIs are just memory writes */ default: return 0; return false; } } Loading Loading @@ -1609,6 +1608,7 @@ static void arm_smmu_remove_device(struct device *dev) } static const struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_init = arm_smmu_domain_init, .domain_destroy = arm_smmu_domain_destroy, .attach_dev = arm_smmu_attach_dev, Loading @@ -1616,7 +1616,6 @@ static const struct iommu_ops arm_smmu_ops = { .map = arm_smmu_map, .unmap = arm_smmu_unmap, .iova_to_phys = arm_smmu_iova_to_phys, .domain_has_cap = arm_smmu_domain_has_cap, .add_device = arm_smmu_add_device, .remove_device = arm_smmu_remove_device, .pgsize_bitmap = (SECTION_SIZE | Loading Loading
drivers/iommu/arm-smmu.c +9 −10 Original line number Diff line number Diff line Loading @@ -1526,20 +1526,19 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); } static int arm_smmu_domain_has_cap(struct iommu_domain *domain, unsigned long cap) static bool arm_smmu_capable(enum iommu_cap cap) { struct arm_smmu_domain *smmu_domain = domain->priv; struct arm_smmu_device *smmu = smmu_domain->smmu; u32 features = smmu ? smmu->features : 0; switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return features & ARM_SMMU_FEAT_COHERENT_WALK; /* * Return true here as the SMMU can always send out coherent * requests. */ return true; case IOMMU_CAP_INTR_REMAP: return 1; /* MSIs are just memory writes */ return true; /* MSIs are just memory writes */ default: return 0; return false; } } Loading Loading @@ -1609,6 +1608,7 @@ static void arm_smmu_remove_device(struct device *dev) } static const struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_init = arm_smmu_domain_init, .domain_destroy = arm_smmu_domain_destroy, .attach_dev = arm_smmu_attach_dev, Loading @@ -1616,7 +1616,6 @@ static const struct iommu_ops arm_smmu_ops = { .map = arm_smmu_map, .unmap = arm_smmu_unmap, .iova_to_phys = arm_smmu_iova_to_phys, .domain_has_cap = arm_smmu_domain_has_cap, .add_device = arm_smmu_add_device, .remove_device = arm_smmu_remove_device, .pgsize_bitmap = (SECTION_SIZE | Loading