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Commit 1fa67c67 authored by Gregory CLEMENT's avatar Gregory CLEMENT
Browse files

gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K 



Document the device tree binding for the gpio controllers found on the
Marvell Armada 7K and Armada 8K SoCs.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent f853e9a0

Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt

+20 −0
Original line number Diff line number Diff line
@@ -64,6 +64,17 @@ mpp17 17 gpio 
mpp18	18	gpio

mpp19	19	gpio, uart0(rxd), sdio(pw_off)



GPIO:

-----

For common binding part and usage, refer to

Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.



Required properties:



- compatible: "marvell,armada-8k-gpio"



- offset: offset address inside the syscon block



Example:

ap_syscon: system-controller@6f4000 {

	compatible = "syscon", "simple-mfd";
@@ -77,4 +88,13 @@ ap_syscon: system-controller@6f4000 { 
	ap_pinctrl: pinctrl {

		compatible = "marvell,ap806-pinctrl";

	};



	ap_gpio: gpio {

		compatible = "marvell,armada-8k-gpio";

		offset = <0x1040>;

		ngpios = <19>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&ap_pinctrl 0 0 19>;

	};

};

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

+23 −1
Original line number Diff line number Diff line
@@ -149,6 +149,18 @@ mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(r 
mpp61	61	gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)

mpp62	62	gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)



GPIO:

-----



For common binding part and usage, refer to

Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.



Required properties:



- compatible: "marvell,armada-8k-gpio"



- offset: offset address inside the syscon block



Example:



cpm_syscon0: system-controller@440000 {
@@ -163,5 +175,15 @@ cpm_syscon0: system-controller@440000 { 
	cpm_pinctrl: pinctrl {

		compatible = "marvell,armada-8k-cpm-pinctrl";

	};



	cpm_gpio1: gpio@100 {

		compatible = "marvell,armada-8k-gpio";

		offset = <0x100>;

		ngpios = <32>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&cpm_pinctrl 0 0 32>;

		status = "disabled";

	};



};

Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

+17 −7
Original line number Diff line number Diff line
@@ -2,17 +2,27 @@ 


Required properties:



- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"

  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for

  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada

  370. "marvell,mv78200-gpio" should be used for the Discovery

  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP

  SoCs (MV78230, MV78260, MV78460).

- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",

  "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".



    "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,

    Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"

    should be used for the Discovery MV78200.



    "marvel,armadaxp-gpio" should be used for all Armada XP SoCs

    (MV78230, MV78260, MV78460).



    "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K

    SoCs (either from AP or CP), see

    Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

    and

    Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt

    for specific details about the offset property.



- reg: Address and length of the register set for the device. Only one

  entry is expected, except for the "marvell,armadaxp-gpio" variant

  for which two entries are expected: one for the general registers,

  one for the per-cpu registers.

  one for the per-cpu registers. Not used for marvell,armada-8k-gpio.



- interrupts: The list of interrupts that are used for all the pins

  managed by this GPIO bank. There can be more than one interrupt