Loading drivers/media/platform/msm/vidc/venus_hfi.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1237,6 +1237,7 @@ static inline int __boot_firmware(struct venus_hfi_device *device) /* Enable interrupt before sending commands to venus */ /* Enable interrupt before sending commands to venus */ __write_register(device, VIDC_CPU_CS_H2XSOFTINTEN, 0x1); __write_register(device, VIDC_CPU_CS_H2XSOFTINTEN, 0x1); __write_register(device, VIDC_CPU_CS_X2RPMh, 0x0); return rc; return rc; } } Loading drivers/media/platform/msm/vidc/vidc_hfi_io.h +9 −0 Original line number Original line Diff line number Diff line Loading @@ -61,6 +61,15 @@ #define VIDC_CPU_CS_SCIBARG3 (VIDC_CPU_CS_BASE_OFFS + 0x6C) #define VIDC_CPU_CS_SCIBARG3 (VIDC_CPU_CS_BASE_OFFS + 0x6C) /* FAL10 Feature Control */ #define VIDC_CPU_CS_X2RPMh (VIDC_CPU_CS_BASE_OFFS + 0x168) #define VIDC_CPU_CS_X2RPMh_MASK0_BMSK 0x1 #define VIDC_CPU_CS_X2RPMh_MASK0_SHFT 0x0 #define VIDC_CPU_CS_X2RPMh_MASK1_BMSK 0x2 #define VIDC_CPU_CS_X2RPMh_MASK1_SHFT 0x1 #define VIDC_CPU_CS_X2RPMh_SWOVERRIDE_BMSK 0x4 #define VIDC_CPU_CS_X2RPMh_SWOVERRIDE_SHFT 0x3 #define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x150) #define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x150) #define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x1 #define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x1 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0x0 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0x0 Loading Loading
drivers/media/platform/msm/vidc/venus_hfi.c +1 −0 Original line number Original line Diff line number Diff line Loading @@ -1237,6 +1237,7 @@ static inline int __boot_firmware(struct venus_hfi_device *device) /* Enable interrupt before sending commands to venus */ /* Enable interrupt before sending commands to venus */ __write_register(device, VIDC_CPU_CS_H2XSOFTINTEN, 0x1); __write_register(device, VIDC_CPU_CS_H2XSOFTINTEN, 0x1); __write_register(device, VIDC_CPU_CS_X2RPMh, 0x0); return rc; return rc; } } Loading
drivers/media/platform/msm/vidc/vidc_hfi_io.h +9 −0 Original line number Original line Diff line number Diff line Loading @@ -61,6 +61,15 @@ #define VIDC_CPU_CS_SCIBARG3 (VIDC_CPU_CS_BASE_OFFS + 0x6C) #define VIDC_CPU_CS_SCIBARG3 (VIDC_CPU_CS_BASE_OFFS + 0x6C) /* FAL10 Feature Control */ #define VIDC_CPU_CS_X2RPMh (VIDC_CPU_CS_BASE_OFFS + 0x168) #define VIDC_CPU_CS_X2RPMh_MASK0_BMSK 0x1 #define VIDC_CPU_CS_X2RPMh_MASK0_SHFT 0x0 #define VIDC_CPU_CS_X2RPMh_MASK1_BMSK 0x2 #define VIDC_CPU_CS_X2RPMh_MASK1_SHFT 0x1 #define VIDC_CPU_CS_X2RPMh_SWOVERRIDE_BMSK 0x4 #define VIDC_CPU_CS_X2RPMh_SWOVERRIDE_SHFT 0x3 #define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x150) #define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x150) #define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x1 #define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x1 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0x0 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0x0 Loading