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Commit 1f2d6c49 authored by Changhwan Youn's avatar Changhwan Youn Committed by Kukjin Kim
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ARM: S5PV310: Limit the irqs which support cascade interrupt 



The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.

Signed-off-by: default avatarChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b45756f6

arch/arm/mach-s5pv310/cpu.c

+9 −0
Original line number Diff line number Diff line
@@ -127,6 +127,15 @@ void __init s5pv310_init_irq(void) 
	gic_cpu_init(0, S5P_VA_GIC_CPU);



	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {



		/*

		 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are

		 * connected to the interrupt combiner. These irqs

		 * should be initialized to support cascade interrupt.

		 */

		if ((irq >= 40) && !(irq == 51) && !(irq == 53))

			continue;



		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

				COMBINER_IRQ(irq, 0));

		combiner_cascade_irq(irq, IRQ_SPI(irq));