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Commit 1f1d98de authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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cpufreq: qcom-hw: cleanup the driver for HW driver 



Move the current code to support as per the upstream code and bring in
fixes required to support the EPSS driver.

Change-Id: I0a0a0584307b914c62e95ce35c5e47c962d17b23
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 2975d85e

drivers/cpufreq/qcom-cpufreq-hw.c

+232 −249
Original line number Diff line number Diff line
@@ -3,44 +3,43 @@ 
 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/bitfield.h>

#include <linux/cpufreq.h>

#include <linux/cpu_cooling.h>

#include <linux/energy_model.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>

#include <linux/pm_opp.h>

#include <linux/energy_model.h>

#include <linux/sched.h>

#include <linux/cpu_cooling.h>

#include <linux/slab.h>



#define LUT_MAX_ENTRIES			40U

#define CORE_COUNT_VAL(val)		(((val) & (GENMASK(18, 16))) >> 16)

#define LUT_SRC				GENMASK(31, 30)

#define LUT_L_VAL			GENMASK(7, 0)

#define LUT_CORE_COUNT			GENMASK(18, 16)

#define LUT_VOLT			GENMASK(11, 0)

#define LUT_ROW_SIZE			32

#define CLK_HW_DIV			2

#define CYCLE_CNTR_OFFSET(c, m)		((c - cpumask_first(m) + 1) * 4)



enum {

	REG_ENABLE,

	REG_FREQ_LUT_TABLE,

	REG_VOLT_LUT_TABLE,

	REG_FREQ_LUT,

	REG_VOLT_LUT,

	REG_PERF_STATE,

	REG_CYCLE_CNTR,



	REG_ARRAY_SIZE,

};



static unsigned long cpu_hw_rate, xo_rate;

static struct platform_device *global_pdev;

static const u16 *offsets;

static unsigned int lut_row_size = LUT_ROW_SIZE;



struct cpufreq_qcom {

	struct cpufreq_frequency_table *table;

	void __iomem *reg_bases[REG_ARRAY_SIZE];

	cpumask_t related_cpus;

	unsigned int max_cores;

	unsigned long xo_rate;

	unsigned long cpu_hw_rate;

};



struct cpufreq_counter {

	u64 total_cycle_counter;

	u32 prev_cycle_counter;
@@ -49,32 +48,41 @@ struct cpufreq_counter { 


static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = {

	[REG_ENABLE]		= 0x0,

	[REG_FREQ_LUT_TABLE]	= 0x100,

	[REG_VOLT_LUT_TABLE]	= 0x200,

	[REG_FREQ_LUT]		= 0x110,

	[REG_VOLT_LUT]		= 0x114,

	[REG_PERF_STATE]	= 0x920,

	[REG_CYCLE_CNTR]	= 0x9c0,

};



static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = {

	[REG_ENABLE]		= 0x0,

	[REG_FREQ_LUT]		= 0x100,

	[REG_VOLT_LUT]		= 0x200,

	[REG_PERF_STATE]	= 0x320,

	[REG_CYCLE_CNTR]	= 0x3c4,

};





static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS];

static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS];



static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu)

{

	struct cpufreq_counter *cpu_counter;

	struct cpufreq_qcom *cpu_domain;

	struct cpufreq_policy *policy;

	u64 cycle_counter_ret;

	unsigned long flags;

	u16 offset;

	u32 val;



	cpu_domain = qcom_freq_domain_map[cpu];

	policy = cpufreq_cpu_get_raw(cpu);

	if (!policy)

		return 0;



	cpu_counter = &qcom_cpufreq_counter[cpu];

	spin_lock_irqsave(&cpu_counter->lock, flags);



	offset = CYCLE_CNTR_OFFSET(cpu, &cpu_domain->related_cpus);

	val = readl_relaxed_no_log(cpu_domain->reg_bases[REG_CYCLE_CNTR] +

				   offset);

	offset = CYCLE_CNTR_OFFSET(cpu, policy->related_cpus);

	val = readl_relaxed_no_log(policy->driver_data +

				    offsets[REG_CYCLE_CNTR] + offset);



	if (val < cpu_counter->prev_cycle_counter) {

		/* Handle counter overflow */
@@ -86,6 +94,7 @@ static u64 qcom_cpufreq_get_cpu_cycle_counter(int cpu) 
			cpu_counter->prev_cycle_counter;

		cpu_counter->prev_cycle_counter = val;

	}



	cycle_counter_ret = cpu_counter->total_cycle_counter;

	spin_unlock_irqrestore(&cpu_counter->lock, flags);
@@ -96,9 +105,9 @@ static int 
qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,

			     unsigned int index)

{

	struct cpufreq_qcom *c = policy->driver_data;

	void __iomem *perf_state_reg = policy->driver_data;



	writel_relaxed(index, c->reg_bases[REG_PERF_STATE]);

	writel_relaxed(index, perf_state_reg + offsets[REG_PERF_STATE]);

	arch_set_freq_scale(policy->related_cpus,

			    policy->freq_table[index].frequency,

			    policy->cpuinfo.max_freq);
@@ -108,7 +117,7 @@ qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, 


static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)

{

	struct cpufreq_qcom *c;

	void __iomem *perf_state_reg;

	struct cpufreq_policy *policy;

	unsigned int index;
@@ -116,9 +125,9 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) 
	if (!policy)

		return 0;



	c = policy->driver_data;

	perf_state_reg = policy->driver_data + offsets[REG_PERF_STATE];



	index = readl_relaxed(c->reg_bases[REG_PERF_STATE]);

	index = readl_relaxed(perf_state_reg);

	index = min(index, LUT_MAX_ENTRIES - 1);



	return policy->freq_table[index].frequency;
@@ -128,167 +137,87 @@ static unsigned int 
qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,

			    unsigned int target_freq)

{

	struct cpufreq_qcom *c = policy->driver_data;

	void __iomem *perf_state_reg = policy->driver_data +

					offsets[REG_PERF_STATE];

	int index;



	index = policy->cached_resolved_idx;

	if (index < 0)

		return 0;



	writel_relaxed(index, c->reg_bases[REG_PERF_STATE]);

	writel_relaxed(index, perf_state_reg);



	return policy->freq_table[index].frequency;

}



static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)

{

	struct em_data_callback em_cb = EM_DATA_CB(of_dev_pm_opp_get_cpu_power);

	struct cpufreq_qcom *c;

	struct device *cpu_dev;

	int ret;



	cpu_dev = get_cpu_device(policy->cpu);

	if (!cpu_dev) {

		pr_err("%s: failed to get cpu%d device\n", __func__,

				policy->cpu);

		return -ENODEV;

	}



	c = qcom_freq_domain_map[policy->cpu];

	if (!c) {

		pr_err("No scaling support for CPU%d\n", policy->cpu);

		return -ENODEV;

	}



	cpumask_copy(policy->cpus, &c->related_cpus);



	ret = dev_pm_opp_get_opp_count(cpu_dev);

	if (ret <= 0)

		dev_err(cpu_dev, "OPP table is not ready\n");



	policy->fast_switch_possible = true;

	policy->freq_table = c->table;

	policy->driver_data = c;

	policy->dvfs_possible_from_any_cpu = true;



	em_register_perf_domain(policy->cpus, ret, &em_cb);



	return 0;

}



static struct freq_attr *qcom_cpufreq_hw_attr[] = {

	&cpufreq_freq_attr_scaling_available_freqs,

	&cpufreq_freq_attr_scaling_boost_freqs,

	NULL

};



static void qcom_cpufreq_ready(struct cpufreq_policy *policy)

static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,

				    struct cpufreq_policy *policy,

				    u32 max_cores)

{

	static struct thermal_cooling_device *cdev[NR_CPUS];

	struct device_node *np;

	unsigned int cpu = policy->cpu;



	if (cdev[cpu])

		return;



	np = of_cpu_device_node_get(cpu);

	if (WARN_ON(!np))

		return;



	/*

	 * For now, just loading the cooling device;

	 * thermal DT code takes care of matching them.

	 */

	if (of_find_property(np, "#cooling-cells", NULL)) {

		cdev[cpu] = of_cpufreq_cooling_register(policy);

		if (IS_ERR(cdev[cpu])) {

			pr_err("running cpufreq for CPU%d without cooling dev: %ld\n",

			       cpu, PTR_ERR(cdev[cpu]));

			cdev[cpu] = NULL;

		}

	}



	of_node_put(np);

}



static struct cpufreq_driver cpufreq_qcom_hw_driver = {

	.flags		= CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |

			  CPUFREQ_HAVE_GOVERNOR_PER_POLICY,

	.verify		= cpufreq_generic_frequency_table_verify,

	.target_index	= qcom_cpufreq_hw_target_index,

	.get		= qcom_cpufreq_hw_get,

	.init		= qcom_cpufreq_hw_cpu_init,

	.fast_switch    = qcom_cpufreq_hw_fast_switch,

	.name		= "qcom-cpufreq-hw",

	.attr		= qcom_cpufreq_hw_attr,

	.boost_enabled	= true,

	.ready		= qcom_cpufreq_ready,

};

	u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq;

	u32 volt;

	struct cpufreq_frequency_table *table;

	void __iomem *base = policy->driver_data;



static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev,

				    struct cpufreq_qcom *c)

{

	struct device *dev = &pdev->dev;

	void __iomem *base_freq, *base_volt;

	u32 data, src, lval, i, core_count, prev_cc, prev_freq, cur_freq, volt;

	unsigned long cpu;



	c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,

				sizeof(*c->table), GFP_KERNEL);

	if (!c->table)

	table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);

	if (!table)

		return -ENOMEM;



	base_freq = c->reg_bases[REG_FREQ_LUT_TABLE];

	base_volt = c->reg_bases[REG_VOLT_LUT_TABLE];



	for (i = 0; i < LUT_MAX_ENTRIES; i++) {

		data = readl_relaxed(base_freq + i * LUT_ROW_SIZE);

		src = (data & GENMASK(31, 30)) >> 30;

		lval = data & GENMASK(7, 0);

		core_count = CORE_COUNT_VAL(data);

		data = readl_relaxed(base + offsets[REG_FREQ_LUT] +

				      i * lut_row_size);

		src = FIELD_GET(LUT_SRC, data);

		lval = FIELD_GET(LUT_L_VAL, data);

		core_count = FIELD_GET(LUT_CORE_COUNT, data);



		data = readl_relaxed(base_volt + i * LUT_ROW_SIZE);

		volt = (data & GENMASK(11, 0)) * 1000;

		data = readl_relaxed(base + offsets[REG_VOLT_LUT] +

				      i * lut_row_size);

		volt = FIELD_GET(LUT_VOLT, data) * 1000;



		if (src)

			c->table[i].frequency = c->xo_rate * lval / 1000;

			freq = xo_rate * lval / 1000;

		else

			c->table[i].frequency = c->cpu_hw_rate / 1000;



		cur_freq = c->table[i].frequency;



		dev_dbg(dev, "index=%d freq=%d, core_count %d\n",

			i, c->table[i].frequency, core_count);

			freq = cpu_hw_rate / 1000;



		if (core_count != c->max_cores)

			cur_freq = CPUFREQ_ENTRY_INVALID;

		if (freq != prev_freq && core_count == max_cores) {

			table[i].frequency = freq;

			dev_pm_opp_add(cpu_dev, freq * 1000, volt);

			dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,

				freq, core_count);

		} else {

			table[i].frequency = CPUFREQ_ENTRY_INVALID;

		}



		/*

		 * Two of the same frequencies with the same core counts means

		 * end of table.

		 */

		if (i > 0 && c->table[i - 1].frequency ==

		   c->table[i].frequency && prev_cc == core_count) {

			struct cpufreq_frequency_table *prev = &c->table[i - 1];

		if (i > 0 && prev_freq == freq && prev_cc == core_count) {

			struct cpufreq_frequency_table *prev = &table[i - 1];



			if (prev_freq == CPUFREQ_ENTRY_INVALID)

			if (prev_cc != max_cores) {

				prev->frequency = prev_freq;

				prev->flags = CPUFREQ_BOOST_FREQ;

				dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt);

			}



			break;

		}



		prev_cc = core_count;

		prev_freq = cur_freq;

		prev_freq = freq;



		cur_freq *= 1000;

		for_each_cpu(cpu, &c->related_cpus)

			dev_pm_opp_add(get_cpu_device(cpu), cur_freq, volt);

		freq *= 1000;

	}



	c->table[i].frequency = CPUFREQ_TABLE_END;

	table[i].frequency = CPUFREQ_TABLE_END;

	policy->freq_table = table;

	dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);



	return 0;

}



static int qcom_get_related_cpus(int index, struct cpumask *m)

static void qcom_get_related_cpus(int index, struct cpumask *m)

{

	struct device_node *cpu_np;

	struct of_phandle_args args;
@@ -300,7 +229,8 @@ static int qcom_get_related_cpus(int index, struct cpumask *m) 
			continue;



		ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",

				"#freq-domain-cells", 0, &args);

						 "#freq-domain-cells", 0,

						 &args);

		of_node_put(cpu_np);

		if (ret < 0)

			continue;
@@ -308,168 +238,214 @@ static int qcom_get_related_cpus(int index, struct cpumask *m) 
		if (index == args.args[0])

			cpumask_set_cpu(cpu, m);

	}



	return 0;

}



static int qcom_cpu_resources_init(struct platform_device *pdev,

				   unsigned int cpu, int index,

				   unsigned int max_cores,

				   unsigned long xo_rate,

				   unsigned long cpu_hw_rate)

static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)

{

	struct cpufreq_qcom *c;

	struct device *dev = &global_pdev->dev;

	struct of_phandle_args args;

	struct device_node *cpu_np;

	struct device *cpu_dev;

	struct resource *res;

	struct device *dev = &pdev->dev;

	const u16 *offsets;

	int ret, i, cpu_r;

	void __iomem *base;

	int ret, index;



	if (qcom_freq_domain_map[cpu])

		return 0;

	cpu_dev = get_cpu_device(policy->cpu);

	if (!cpu_dev) {

		pr_err("%s: failed to get cpu%d device\n", __func__,

		       policy->cpu);

		return -ENODEV;

	}



	cpu_np = of_cpu_device_node_get(policy->cpu);

	if (!cpu_np)

		return -EINVAL;



	c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL);

	if (!c)

	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",

					 "#freq-domain-cells", 0, &args);

	of_node_put(cpu_np);

	if (ret)

		return ret;



	index = args.args[0];



	res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);

	if (!res)

		return -ENODEV;



	base = devm_ioremap(dev, res->start, resource_size(res));

	if (!base)

		return -ENOMEM;



	offsets = of_device_get_match_data(&pdev->dev);

	offsets = of_device_get_match_data(dev);

	if (!offsets)

		return -EINVAL;



	res = platform_get_resource(pdev, IORESOURCE_MEM, index);

	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base))

		return PTR_ERR(base);



	for (i = REG_ENABLE; i < REG_ARRAY_SIZE; i++)

		c->reg_bases[i] = base + offsets[i];



	if (!of_property_read_bool(dev->of_node, "qcom,skip-enable-check")) {

		/* HW should be in enabled state to proceed */

		if (!(readl_relaxed(c->reg_bases[REG_ENABLE]) & 0x1)) {

		if (!(readl_relaxed(base +  offsets[REG_ENABLE]) & 0x1)) {

			dev_err(dev, "Domain-%d cpufreq hardware not enabled\n",

				 index);

			return -ENODEV;

		}

	}



	ret = qcom_get_related_cpus(index, &c->related_cpus);

	if (ret) {

	qcom_get_related_cpus(index, policy->cpus);

	if (!cpumask_weight(policy->cpus)) {

		dev_err(dev, "Domain-%d failed to get related CPUs\n", index);

		return ret;

		ret = -ENOENT;

		goto error;

	}



	c->max_cores = max_cores;

	if (!c->max_cores)

		return -ENOENT;

	policy->driver_data = base;



	c->xo_rate = xo_rate;

	c->cpu_hw_rate = cpu_hw_rate;



	ret = qcom_cpufreq_hw_read_lut(pdev, c);

	ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, args.args[1]);

	if (ret) {

		dev_err(dev, "Domain-%d failed to read LUT\n", index);

		return ret;

		goto error;

	}



	for_each_cpu(cpu_r, &c->related_cpus)

		qcom_freq_domain_map[cpu_r] = c;



	return 0;

	ret = dev_pm_opp_get_opp_count(cpu_dev);

	if (ret <= 0) {

		dev_err(cpu_dev, "Failed to add OPPs\n");

		ret = -ENODEV;

		goto error;

	}



static int qcom_resources_init(struct platform_device *pdev)

{

	struct device_node *cpu_np;

	struct of_phandle_args args;

	struct clk *clk;

	unsigned int cpu;

	unsigned long xo_rate, cpu_hw_rate;

	int ret;



	clk = devm_clk_get(&pdev->dev, "xo");

	if (IS_ERR(clk))

		return PTR_ERR(clk);

	dev_pm_opp_of_register_em(policy->cpus);



	xo_rate = clk_get_rate(clk);

	policy->fast_switch_possible = true;

	policy->dvfs_possible_from_any_cpu = true;



	devm_clk_put(&pdev->dev, clk);

	return 0;

error:

	devm_iounmap(dev, base);

	return ret;

}



	clk = devm_clk_get(&pdev->dev, "alternate");

	if (IS_ERR(clk))

		return PTR_ERR(clk);

static void qcom_cpufreq_ready(struct cpufreq_policy *policy)

{

	static struct thermal_cooling_device *cdev[NR_CPUS];

	struct device_node *np;

	unsigned int cpu = policy->cpu;



	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;

	if (cdev[cpu])

		return;



	devm_clk_put(&pdev->dev, clk);

	np = of_cpu_device_node_get(cpu);

	if (WARN_ON(!np))

		return;



	of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size",

			      &lut_row_size);

	/*

	 * For now, just loading the cooling device;

	 * thermal DT code takes care of matching them.

	 */

	if (of_find_property(np, "#cooling-cells", NULL)) {

		cdev[cpu] = of_cpufreq_cooling_register(policy);

		if (IS_ERR(cdev[cpu])) {

			pr_err("running cpufreq for CPU%d without cooling dev: %ld\n",

			       cpu, PTR_ERR(cdev[cpu]));

			cdev[cpu] = NULL;

		}

	}



	for_each_possible_cpu(cpu) {

		cpu_np = of_cpu_device_node_get(cpu);

		if (!cpu_np) {

			dev_dbg(&pdev->dev, "Failed to get cpu %d device\n",

				cpu);

			continue;

	of_node_put(np);

}



		ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",

				"#freq-domain-cells", 0, &args);

		if (ret < 0)

			return ret;

static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)

{

	struct device *cpu_dev = get_cpu_device(policy->cpu);

	void __iomem *base = policy->driver_data;



		ret = qcom_cpu_resources_init(pdev, cpu, args.args[0],

					      args.args[1], xo_rate,

					      cpu_hw_rate);

		if (ret)

			return ret;

	}

	dev_pm_opp_remove_all_dynamic(cpu_dev);

	kfree(policy->freq_table);

	devm_iounmap(&global_pdev->dev, base);



	return 0;

}



static struct freq_attr *qcom_cpufreq_hw_attr[] = {

	&cpufreq_freq_attr_scaling_available_freqs,

	&cpufreq_freq_attr_scaling_boost_freqs,

	NULL

};



static struct cpufreq_driver cpufreq_qcom_hw_driver = {

	.flags		= CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |

			  CPUFREQ_HAVE_GOVERNOR_PER_POLICY,

	.verify		= cpufreq_generic_frequency_table_verify,

	.target_index	= qcom_cpufreq_hw_target_index,

	.get		= qcom_cpufreq_hw_get,

	.init		= qcom_cpufreq_hw_cpu_init,

	.exit		= qcom_cpufreq_hw_cpu_exit,

	.fast_switch    = qcom_cpufreq_hw_fast_switch,

	.name		= "qcom-cpufreq-hw",

	.attr		= qcom_cpufreq_hw_attr,

	.boost_enabled	= true,

	.ready		= qcom_cpufreq_ready,

};



static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)

{

	int rc;

	struct cpu_cycle_counter_cb cycle_counter_cb = {

		.get_cpu_cycle_counter = qcom_cpufreq_get_cpu_cycle_counter,

	};

	struct clk *clk;

	int ret;



	/* Get the bases of cpufreq for domains */

	rc = qcom_resources_init(pdev);

	if (rc) {

		dev_err(&pdev->dev, "CPUFreq resource init failed\n");

		return rc;

	}

	clk = clk_get(&pdev->dev, "xo");

	if (IS_ERR(clk))

		return PTR_ERR(clk);



	xo_rate = clk_get_rate(clk);

	clk_put(clk);



	clk = clk_get(&pdev->dev, "alternate");

	if (IS_ERR(clk))

		return PTR_ERR(clk);



	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;

	clk_put(clk);



	of_property_read_u32(pdev->dev.of_node, "qcom,lut-row-size",

			     &lut_row_size);



	global_pdev = pdev;



	rc = cpufreq_register_driver(&cpufreq_qcom_hw_driver);

	if (rc) {

	ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);

	if (ret) {

		dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");

		return rc;

		return ret;

	}



	rc = register_cpu_cycle_counter_cb(&cycle_counter_cb);

	if (rc) {

	ret = register_cpu_cycle_counter_cb(&cycle_counter_cb);

	if (ret) {

		dev_err(&pdev->dev, "cycle counter cb failed to register\n");

		return rc;

		return ret;

	}



	dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");

	of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

	dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");



	return 0;

	return ret;

}



static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)

{

	return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);

}



static const struct of_device_id qcom_cpufreq_hw_match[] = {

	{ .compatible = "qcom,cpufreq-hw", .data = &cpufreq_qcom_std_offsets },

	{ .compatible = "qcom,cpufreq-hw-epss",

					   .data = &cpufreq_qcom_std_offsets },

				    .data = &cpufreq_qcom_epss_std_offsets },

	{}

};

MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);



static struct platform_driver qcom_cpufreq_hw_driver = {

	.probe = qcom_cpufreq_hw_driver_probe,

	.remove = qcom_cpufreq_hw_driver_remove,

	.driver = {

		.name = "qcom-cpufreq-hw",

		.of_match_table = qcom_cpufreq_hw_match,
@@ -482,4 +458,11 @@ static int __init qcom_cpufreq_hw_init(void) 
}

subsys_initcall(qcom_cpufreq_hw_init);



MODULE_DESCRIPTION("QCOM firmware-based CPU Frequency driver");
 
static void __exit qcom_cpufreq_hw_exit(void)

{

	platform_driver_unregister(&qcom_cpufreq_hw_driver);

}

module_exit(qcom_cpufreq_hw_exit);



MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");

MODULE_LICENSE("GPL v2");