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Commit 1f1bc822 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Greg Kroah-Hartman
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x86/cpu: Sanitize FAM6_ATOM naming 

commit f2c4db1bd80720cd8cb2a5aa220d9bc9f374f04e upstream

Going primarily by:

  https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors



with additional information gleaned from other related pages; notably:

 - Bonnell shrink was called Saltwell
 - Moorefield is the Merriefield refresh which makes it Airmont

The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE

  for i in `git grep -l FAM6_ATOM` ; do
	sed -i  -e 's/ATOM_PINEVIEW/ATOM_BONNELL/g'		\
		-e 's/ATOM_LINCROFT/ATOM_BONNELL_MID/'		\
		-e 's/ATOM_PENWELL/ATOM_SALTWELL_MID/g'		\
		-e 's/ATOM_CLOVERVIEW/ATOM_SALTWELL_TABLET/g'	\
		-e 's/ATOM_CEDARVIEW/ATOM_SALTWELL/g'		\
		-e 's/ATOM_SILVERMONT1/ATOM_SILVERMONT/g'	\
		-e 's/ATOM_SILVERMONT2/ATOM_SILVERMONT_X/g'	\
		-e 's/ATOM_MERRIFIELD/ATOM_SILVERMONT_MID/g'	\
		-e 's/ATOM_MOOREFIELD/ATOM_AIRMONT_MID/g'	\
		-e 's/ATOM_DENVERTON/ATOM_GOLDMONT_X/g'		\
		-e 's/ATOM_GEMINI_LAKE/ATOM_GOLDMONT_PLUS/g' ${i}
  done

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: dave.hansen@linux.intel.com
Cc: len.brown@intel.com
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 34aae15c

arch/x86/events/intel/core.c

+11 −9
Original line number Diff line number Diff line
@@ -4132,11 +4132,11 @@ __init int intel_pmu_init(void) 
		name = "nehalem";

		break;



	case INTEL_FAM6_ATOM_PINEVIEW:

	case INTEL_FAM6_ATOM_LINCROFT:

	case INTEL_FAM6_ATOM_PENWELL:

	case INTEL_FAM6_ATOM_CLOVERVIEW:

	case INTEL_FAM6_ATOM_CEDARVIEW:

	case INTEL_FAM6_ATOM_BONNELL:

	case INTEL_FAM6_ATOM_BONNELL_MID:

	case INTEL_FAM6_ATOM_SALTWELL:

	case INTEL_FAM6_ATOM_SALTWELL_MID:

	case INTEL_FAM6_ATOM_SALTWELL_TABLET:

		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -4149,9 +4149,11 @@ __init int intel_pmu_init(void) 
		name = "bonnell";

		break;



	case INTEL_FAM6_ATOM_SILVERMONT1:

	case INTEL_FAM6_ATOM_SILVERMONT2:

	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_X:

	case INTEL_FAM6_ATOM_SILVERMONT_MID:

	case INTEL_FAM6_ATOM_AIRMONT:

	case INTEL_FAM6_ATOM_AIRMONT_MID:

		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,

			sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
@@ -4170,7 +4172,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_DENVERTON:

	case INTEL_FAM6_ATOM_GOLDMONT_X:

		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
@@ -4196,7 +4198,7 @@ __init int intel_pmu_init(void) 
		name = "goldmont";

		break;



	case INTEL_FAM6_ATOM_GEMINI_LAKE:

	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,

arch/x86/events/intel/cstate.c

+4 −4
Original line number Diff line number Diff line
@@ -559,8 +559,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT1, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT2, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT,     slm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE,   snb_cstates),
@@ -581,9 +581,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),

	{ },

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

arch/x86/events/intel/rapl.c

+2 −2
Original line number Diff line number Diff line
@@ -777,9 +777,9 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { 
	X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,  skl_rapl_init),



	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_X, hsw_rapl_init),



	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GEMINI_LAKE, hsw_rapl_init),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_PLUS, hsw_rapl_init),

	{},

};

arch/x86/events/msr.c

+4 −4
Original line number Diff line number Diff line
@@ -69,14 +69,14 @@ static bool test_intel(int idx) 
	case INTEL_FAM6_BROADWELL_GT3E:

	case INTEL_FAM6_BROADWELL_X:



	case INTEL_FAM6_ATOM_SILVERMONT1:

	case INTEL_FAM6_ATOM_SILVERMONT2:

	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_X:

	case INTEL_FAM6_ATOM_AIRMONT:



	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_DENVERTON:

	case INTEL_FAM6_ATOM_GOLDMONT_X:



	case INTEL_FAM6_ATOM_GEMINI_LAKE:

	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:



	case INTEL_FAM6_XEON_PHI_KNL:

	case INTEL_FAM6_XEON_PHI_KNM:

arch/x86/include/asm/intel-family.h

+17 −16
Original line number Diff line number Diff line
@@ -8,9 +8,6 @@ 
 * The "_X" parts are generally the EP and EX Xeons, or the

 * "Extreme" ones, like Broadwell-E.

 *

 * Things ending in "2" are usually because we have no better

 * name for them.  There's no processor called "SILVERMONT2".

 *

 * While adding a new CPUID for a new microarchitecture, add a new

 * group to keep logically sorted out in chronological order. Within

 * that group keep the CPUID for the variants sorted by model number.
@@ -59,19 +56,23 @@ 


/* "Small Core" Processors (Atom) */



#define INTEL_FAM6_ATOM_PINEVIEW	0x1C

#define INTEL_FAM6_ATOM_LINCROFT	0x26

#define INTEL_FAM6_ATOM_PENWELL		0x27

#define INTEL_FAM6_ATOM_CLOVERVIEW	0x35

#define INTEL_FAM6_ATOM_CEDARVIEW	0x36

#define INTEL_FAM6_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT / Valleyview */

#define INTEL_FAM6_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */

#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* CherryTrail / Braswell */

#define INTEL_FAM6_ATOM_MERRIFIELD	0x4A /* Tangier */

#define INTEL_FAM6_ATOM_MOOREFIELD	0x5A /* Anniedale */

#define INTEL_FAM6_ATOM_GOLDMONT	0x5C

#define INTEL_FAM6_ATOM_DENVERTON	0x5F /* Goldmont Microserver */

#define INTEL_FAM6_ATOM_GEMINI_LAKE	0x7A

#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */

#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */



#define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */

#define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */

#define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */



#define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */

#define INTEL_FAM6_ATOM_SILVERMONT_X	0x4D /* Avaton, Rangely */

#define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */



#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */

#define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */



#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */

#define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */

#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */



/* Xeon Phi */