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Commit 1f0cf89b authored by Ilan Tayari's avatar Ilan Tayari Committed by David S. Miller
Browse files

net/mlx5: Add FPGA QP error event 



The FPGA queue pair (QP) event fires whenever a QP on the FPGA
transitions to the error state.

At this stage, this event is unrecoverable, it may become recoverable
in the future.

Signed-off-by: default avatarIlan Tayari <ilant@mellanox.com>
Signed-off-by: default avatarAdi Nissim <adin@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1865ea9a

drivers/net/ethernet/mellanox/mlx5/core/eq.c

+5 −2
Original line number Diff line number Diff line
@@ -164,6 +164,8 @@ static const char *eqe_type_str(u8 type) 
		return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";

	case MLX5_EVENT_TYPE_FPGA_ERROR:

		return "MLX5_EVENT_TYPE_FPGA_ERROR";

	case MLX5_EVENT_TYPE_FPGA_QP_ERROR:

		return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";

	case MLX5_EVENT_TYPE_GENERAL_EVENT:

		return "MLX5_EVENT_TYPE_GENERAL_EVENT";

	default:
@@ -563,6 +565,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr) 
			break;



		case MLX5_EVENT_TYPE_FPGA_ERROR:

		case MLX5_EVENT_TYPE_FPGA_QP_ERROR:

			mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);

			break;
@@ -842,11 +845,11 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev) 
		async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);



	if (MLX5_CAP_GEN(dev, fpga))

		async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);

		async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |

				    (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);

	if (MLX5_CAP_GEN_MAX(dev, dct))

		async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);





	if (MLX5_CAP_GEN(dev, temp_warn_event))

		async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);

include/linux/mlx5/device.h

+1 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ enum mlx5_event { 
	MLX5_EVENT_TYPE_DCT_DRAINED        = 0x1c,



	MLX5_EVENT_TYPE_FPGA_ERROR         = 0x20,

	MLX5_EVENT_TYPE_FPGA_QP_ERROR      = 0x21,

};



enum {

include/linux/mlx5/mlx5_ifc.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ enum { 
	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,

	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,

	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,

	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21

};



enum {

include/linux/mlx5/mlx5_ifc_fpga.h

+16 −0
Original line number Diff line number Diff line
@@ -470,6 +470,22 @@ struct mlx5_ifc_ipsec_counters_bits { 
	u8         dropped_cmd[0x40];

};



enum {

	MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED  = 0x1,

	MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED            = 0x2,

};



struct mlx5_ifc_fpga_qp_error_event_bits {

	u8         reserved_at_0[0x40];



	u8         reserved_at_40[0x18];

	u8         syndrome[0x8];



	u8         reserved_at_60[0x60];



	u8         reserved_at_c0[0x8];

	u8         fpga_qpn[0x18];

};

enum mlx5_ifc_fpga_ipsec_response_syndrome {

	MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0,

	MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,