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Commit 1eed29df authored by Haavard Skinnemoen's avatar Haavard Skinnemoen Committed by Linus Torvalds
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atmel_spi throughput improvement 



Don't insert (undesirable) delays between consecutive words (DLYBCT) or when
activating chipselects (DLYBS).

Removing the between-word delays improves the performance of bulk transfers
(such as mtd_dataflash, m25p80, mmc_spi) significantly.  In one test, the
improvement was a factor of more than eight!

(The large DLYBCT value came from the legacy at91 SPI driver, and it's not
clear why it used such a huge value.)

Signed-off-by: default avatarHaavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 3c72426f

drivers/spi/atmel_spi.c

+8 −3
Original line number Diff line number Diff line
@@ -490,9 +490,14 @@ static int atmel_spi_setup(struct spi_device *spi) 
	if (!(spi->mode & SPI_CPHA))

		csr |= SPI_BIT(NCPHA);



	/* TODO: DLYBS and DLYBCT */

	csr |= SPI_BF(DLYBS, 10);

	csr |= SPI_BF(DLYBCT, 10);

	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.

	 *

	 * DLYBCT would add delays between words, slowing down transfers.

	 * It could potentially be useful to cope with DMA bottlenecks, but

	 * in those cases it's probably best to just use a lower bitrate.

	 */

	csr |= SPI_BF(DLYBS, 0);

	csr |= SPI_BF(DLYBCT, 0);



	/* chipselect must have been muxed as GPIO (e.g. in board setup) */

	npcs_pin = (unsigned int)spi->controller_data;