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Commit 1ed10691 authored by Brian Norris's avatar Brian Norris
Browse files

Merge tag 'nand/for-4.8' of github.com:linux-nand/linux into mtd 

Pull NAND changes from Boris Brezillon:
"""
This pull request contains only one notable change:
* Addition of the MTK NAND controller driver

And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
"""
parents 7ddf7c1e 8490c03b

Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

+6 −1
Original line number Diff line number Diff line
@@ -46,6 +46,10 @@ Required properties: 
			0 maps to GPMC_WAIT0 pin.

 - gpio-cells:		Must be set to 2



Required properties when using NAND prefetch dma:

 - dmas			GPMC NAND prefetch dma channel

 - dma-names		Must be set to "rxtx"



Timing properties for child nodes. All are optional and default to 0.



 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds
@@ -137,7 +141,8 @@ Example for an AM33xx board: 
		ti,hwmods = "gpmc";

		reg = <0x50000000 0x2000>;

		interrupts = <100>;



		dmas = <&edma 52 0>;

		dma-names = "rxtx";

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ Required properties: 
                         brcm,brcmnand-v6.2

                         brcm,brcmnand-v7.0

                         brcm,brcmnand-v7.1

                         brcm,brcmnand-v7.2

                         brcm,brcmnand

- reg              : the register start and length for NAND register region.

                     (optional) Flash DMA register range (if present)

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ Optional properties: 


		"prefetch-polled"	Prefetch polled mode (default)

		"polled"		Polled mode, without prefetch

		"prefetch-dma"		Prefetch enabled sDMA mode

		"prefetch-dma"		Prefetch enabled DMA mode

		"prefetch-irq"		Prefetch enabled irq mode



 - elm_id:	<deprecated> use "ti,elm-id" instead

Documentation/devicetree/bindings/mtd/mtk-nand.txt

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+160 −0
Original line number Diff line number Diff line 
MTK SoCs NAND FLASH controller (NFC) DT binding



This file documents the device tree bindings for MTK SoCs NAND controllers.

The functional split of the controller requires two drivers to operate:

the nand controller interface driver and the ECC engine driver.



The hardware description for both devices must be captured as device

tree nodes.



1) NFC NAND Controller Interface (NFI):

=======================================



The first part of NFC is NAND Controller Interface (NFI) HW.

Required NFI properties:

- compatible:			Should be "mediatek,mtxxxx-nfc".

- reg:				Base physical address and size of NFI.

- interrupts:			Interrupts of NFI.

- clocks:			NFI required clocks.

- clock-names:			NFI clocks internal name.

- status:			Disabled default. Then set "okay" by platform.

- ecc-engine:			Required ECC Engine node.

- #address-cells:		NAND chip index, should be 1.

- #size-cells:			Should be 0.



Example:



	nandc: nfi@1100d000 {

		compatible = "mediatek,mt2701-nfc";

		reg = <0 0x1100d000 0 0x1000>;

		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pericfg CLK_PERI_NFI>,

			 <&pericfg CLK_PERI_NFI_PAD>;

		clock-names = "nfi_clk", "pad_clk";

		status = "disabled";

		ecc-engine = <&bch>;

		#address-cells = <1>;

		#size-cells = <0>;

        };



Platform related properties, should be set in {platform_name}.dts:

- children nodes:	NAND chips.



Children nodes properties:

- reg:			Chip Select Signal, default 0.

			Set as reg = <0>, <1> when need 2 CS.

Optional:

- nand-on-flash-bbt:	Store BBT on NAND Flash.

- nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)

- nand-ecc-step-size:	Number of data bytes covered by a single ECC step.

			valid values: 512 and 1024.

			1024 is recommended for large page NANDs.

- nand-ecc-strength:	Number of bits to correct per ECC step.

			The valid values that the controller supports are: 4, 6,

			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,

			48, 52, 56, 60.

			The strength should be calculated as follows:

			E = (S - F) * 8 / 14

			S = O / (P / Q)

				E :	nand-ecc-strength.

				S :	spare size per sector.

				F :	FDM size, should be in the range [1,8].

					It is used to store free oob data.

				O :	oob size.

				P :	page size.

				Q :	nand-ecc-step-size.

			If the result does not match any one of the listed

			choices above, please select the smaller valid value from

			the list.

			(otherwise the driver will do the adjustment at runtime)

- pinctrl-names:	Default NAND pin GPIO setting name.

- pinctrl-0:		GPIO setting node.



Example:

	&pio {

		nand_pins_default: nanddefault {

			pins_dat {

				pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,

					 <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,

					 <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,

					 <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,

					 <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,

					 <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,

					 <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,

					 <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,

					 <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;

				input-enable;

				drive-strength = <MTK_DRIVE_8mA>;

				bias-pull-up;

			};



			pins_we {

				pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;

				drive-strength = <MTK_DRIVE_8mA>;

				bias-pull-up = <MTK_PUPD_SET_R1R0_10>;

			};



			pins_ale {

				pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;

				drive-strength = <MTK_DRIVE_8mA>;

				bias-pull-down = <MTK_PUPD_SET_R1R0_10>;

			};

		};

	};



	&nandc {

		status = "okay";

		pinctrl-names = "default";

		pinctrl-0 = <&nand_pins_default>;

		nand@0 {

			reg = <0>;

			nand-on-flash-bbt;

			nand-ecc-mode = "hw";

			nand-ecc-strength = <24>;

			nand-ecc-step-size = <1024>;

		};

	};



NAND chip optional subnodes:

- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt



Example:

	nand@0 {

		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			preloader@0 {

				label = "pl";

				read-only;

				reg = <0x00000000 0x00400000>;

			};

			android@0x00400000 {

				label = "android";

				reg = <0x00400000 0x12c00000>;

			};

		};

	};



2) ECC Engine:

==============



Required BCH properties:

- compatible:	Should be "mediatek,mtxxxx-ecc".

- reg:		Base physical address and size of ECC.

- interrupts:	Interrupts of ECC.

- clocks:	ECC required clocks.

- clock-names:	ECC clocks internal name.

- status:	Disabled default. Then set "okay" by platform.



Example:



	bch: ecc@1100e000 {

		compatible = "mediatek,mt2701-ecc";

		reg = <0 0x1100e000 0 0x1000>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&pericfg CLK_PERI_NFI_ECC>;

		clock-names = "nfiecc_clk";

		status = "disabled";

	};

Documentation/devicetree/bindings/mtd/sunxi-nand.txt

+6 −0
Original line number Diff line number Diff line
@@ -11,10 +11,16 @@ Required properties: 
    * "ahb" : AHB gating clock

    * "mod" : nand controller clock



Optional properties:

- dmas : shall reference DMA channel associated to the NAND controller.

- dma-names : shall be "rxtx".



Optional children nodes:

Children nodes represent the available nand chips.



Optional properties:

- reset : phandle + reset specifier pair

- reset-names : must contain "ahb"

- allwinner,rb : shall contain the native Ready/Busy ids.

 or

- rb-gpios : shall contain the gpios used as R/B pins.