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Commit 1e4db5f2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dce3: switch back to old pll allocation order for discrete 



The order shouldn't matter, but this seems to cause regressions for
certain specific cases.  This should fix it for now.  We probably
need to investigate a proper fix in the next development cycle.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Andy Furniss <andyqos@ukfsn.org>
parent 695ddeb4

drivers/gpu/drm/radeon/atombios_crtc.c

+31 −23
Original line number Diff line number Diff line
@@ -1696,8 +1696,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {

		if (ASIC_IS_AVIVO(rdev)) {

	} else if (ASIC_IS_AVIVO(rdev)) {

		/* in DP mode, the DP ref clock can come from either PPLL

		 * depending on the asic:

		 * DCE3: PPLL1 or PPLL2
@@ -1715,10 +1714,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		}

		/* all other cases */

		pll_in_use = radeon_get_pll_use_mask(crtc);

		/* the order shouldn't matter here, but we probably

		 * need this until we have atomic modeset

		 */

		if (rdev->flags & RADEON_IS_IGP) {

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

		} else {

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

		}

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {
@@ -1726,7 +1735,6 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
		return radeon_crtc->crtc_id;

	}

}

}



void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)

{