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Commit 1d9a17dd authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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ARM: dts: wheat: add Ethernet support 



R8A7792  SoC  doesn't have the  EtherMAC core, so SMSC LAN89218 Ethernet
chip was used instead on the Wheat debug board; this chip is compatible
with SMSC LAN9115 for which  there's a (device  tree aware)  driver.
Describe the chip  in the Wheat device tree unconditionally (the driver
should fail the probe if the debug board isn't connected); enable DHCP and
NFS root in the command line for the kernel boot...

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 5f45cec4

arch/arm/boot/dts/r8a7792-wheat.dts

+37 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
	};



	chosen {

		bootargs = "ignore_loglevel";

		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";

		stdout-path = "serial0:115200n8";

	};
@@ -29,6 +29,31 @@ 
		device_type = "memory";

		reg = <0 0x40000000 0 0x40000000>;

	};



	d3_3v: regulator-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "D3.3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-boot-on;

		regulator-always-on;

	};



	ethernet@18000000 {

		compatible = "smsc,lan89218", "smsc,lan9115";

		reg = <0 0x18000000 0 0x100>;

		phy-mode = "mii";

		interrupt-parent = <&irqc>;

		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;

		smsc,irq-push-pull;

		smsc,save-mac-address;

		reg-io-width = <4>;

		vddvario-supply = <&d3_3v>;

		vdd33a-supply = <&d3_3v>;



		pinctrl-0 = <&lan89218_pins>;

		pinctrl-names = "default";

	};

};



&extal_clk {
@@ -40,6 +65,17 @@ 
		groups = "scif0_data";

		function = "scif0";

	};



	lan89218_pins: lan89218 {

		intc {

			groups = "intc_irq0";

			function = "intc";

		};

		lbsc {

			groups = "lbsc_ex_cs0";

			function = "lbsc";

		};

	};

};



&scif0 {