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Commit 1d96ad64 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-uniphier' into clk-next

* clk-uniphier:
  clk: uniphier: fix DAPLL2 clock rate of Pro5
  clk: uniphier: fix parent of miodmac clock data
parents e8d07fd2 67affb78
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+3 −4
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@
 * GNU General Public License for more details.
 */

#include <linux/stddef.h>

#include "clk-uniphier.h"

#define UNIPHIER_MIO_CLK_SD_FIXED					\
@@ -73,15 +75,12 @@
#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch)				\
	UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)

#define UNIPHIER_MIO_CLK_DMAC(idx)					\
	UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)

const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
	UNIPHIER_MIO_CLK_SD_FIXED,
	UNIPHIER_MIO_CLK_SD(0, 0),
	UNIPHIER_MIO_CLK_SD(1, 1),
	UNIPHIER_MIO_CLK_SD(2, 2),
	UNIPHIER_MIO_CLK_DMAC(7),
	UNIPHIER_CLK_GATE("miodmac", 7, NULL, 0x20, 25),
	UNIPHIER_MIO_CLK_USB2(8, 0),
	UNIPHIER_MIO_CLK_USB2(9, 1),
	UNIPHIER_MIO_CLK_USB2(10, 2),
+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),		/* 2400 MHz */
	UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),	/* 2560 MHz */
	UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125),	/* 2949.12 MHz */
	UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),	/* 2949.12 MHz */
	UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
	UNIPHIER_PRO5_SYS_CLK_NAND(2),