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Commit 1d93ba2a authored by Russell King's avatar Russell King
Browse files

ARM: l2c: tauros2: use descriptive definitions for register bits 



Use descriptive definitions for the Tauros2 register bits, and while
we're here, clean up the "Tauros2: %s line fill burt8." message.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 172f3fcb

arch/arm/mm/cache-tauros2.c

+10 −5
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ 
#include <asm/cputype.h>

#include <asm/hardware/cache-tauros2.h>



/* CP15 PJ4 Control configuration register */

#define CCR_L2C_PREFETCH_DISABLE	BIT(24)

#define CCR_L2C_ECC_ENABLE		BIT(23)

#define CCR_L2C_WAY7_4_DISABLE		BIT(21)

#define CCR_L2C_BURST8_ENABLE		BIT(20)



/*

 * When Tauros2 is used on a CPU that supports the v7 hierarchical
@@ -182,18 +187,18 @@ static void enable_extra_feature(unsigned int features) 
	u = read_extra_features();



	if (features & CACHE_TAUROS2_PREFETCH_ON)

		u &= ~0x01000000;

		u &= ~CCR_L2C_PREFETCH_DISABLE;

	else

		u |= 0x01000000;

		u |= CCR_L2C_PREFETCH_DISABLE;

	pr_info("Tauros2: %s L2 prefetch.\n",

			(features & CACHE_TAUROS2_PREFETCH_ON)

			? "Enabling" : "Disabling");



	if (features & CACHE_TAUROS2_LINEFILL_BURST8)

		u |= 0x00100000;

		u |= CCR_L2C_BURST8_ENABLE;

	else

		u &= ~0x00100000;

	pr_info("Tauros2: %s line fill burt8.\n",

		u &= ~CCR_L2C_BURST8_ENABLE;

	pr_info("Tauros2: %s burst8 line fill.\n",

			(features & CACHE_TAUROS2_LINEFILL_BURST8)

			? "Enabling" : "Disabling");