Loading drivers/char/hw_random/core.c +1 −1 Original line number Diff line number Diff line Loading @@ -429,7 +429,7 @@ static int hwrng_fillfn(void *unused) static void start_khwrngd(void) { hwrng_fill = kthread_run(hwrng_fillfn, NULL, "hwrng"); if (hwrng_fill == ERR_PTR(-ENOMEM)) { if (IS_ERR(hwrng_fill)) { pr_err("hwrng_fill thread creation failed"); hwrng_fill = NULL; } Loading drivers/crypto/ixp4xx_crypto.c +0 −1 Original line number Diff line number Diff line Loading @@ -905,7 +905,6 @@ static int ablk_perform(struct ablkcipher_request *req, int encrypt) crypt->mode |= NPE_OP_NOT_IN_PLACE; /* This was never tested by Intel * for more than one dst buffer, I think. */ BUG_ON(req->dst->length < nbytes); req_ctx->dst = NULL; if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook, flags, DMA_FROM_DEVICE)) Loading drivers/crypto/qat/qat_common/qat_algs.c +16 −8 Original line number Diff line number Diff line Loading @@ -73,7 +73,8 @@ ICP_QAT_HW_CIPHER_KEY_CONVERT, \ ICP_QAT_HW_CIPHER_DECRYPT) static atomic_t active_dev; static DEFINE_MUTEX(algs_lock); static unsigned int active_devs; struct qat_alg_buf { uint32_t len; Loading Loading @@ -1275,7 +1276,10 @@ static struct crypto_alg qat_algs[] = { { int qat_algs_register(void) { if (atomic_add_return(1, &active_dev) == 1) { int ret = 0; mutex_lock(&algs_lock); if (++active_devs == 1) { int i; for (i = 0; i < ARRAY_SIZE(qat_algs); i++) Loading @@ -1284,21 +1288,25 @@ int qat_algs_register(void) CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC : CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; return crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs)); ret = crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs)); } return 0; mutex_unlock(&algs_lock); return ret; } int qat_algs_unregister(void) { if (atomic_sub_return(1, &active_dev) == 0) return crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs)); return 0; int ret = 0; mutex_lock(&algs_lock); if (--active_devs == 0) ret = crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs)); mutex_unlock(&algs_lock); return ret; } int qat_algs_init(void) { atomic_set(&active_dev, 0); crypto_get_default_rng(); return 0; } Loading Loading
drivers/char/hw_random/core.c +1 −1 Original line number Diff line number Diff line Loading @@ -429,7 +429,7 @@ static int hwrng_fillfn(void *unused) static void start_khwrngd(void) { hwrng_fill = kthread_run(hwrng_fillfn, NULL, "hwrng"); if (hwrng_fill == ERR_PTR(-ENOMEM)) { if (IS_ERR(hwrng_fill)) { pr_err("hwrng_fill thread creation failed"); hwrng_fill = NULL; } Loading
drivers/crypto/ixp4xx_crypto.c +0 −1 Original line number Diff line number Diff line Loading @@ -905,7 +905,6 @@ static int ablk_perform(struct ablkcipher_request *req, int encrypt) crypt->mode |= NPE_OP_NOT_IN_PLACE; /* This was never tested by Intel * for more than one dst buffer, I think. */ BUG_ON(req->dst->length < nbytes); req_ctx->dst = NULL; if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook, flags, DMA_FROM_DEVICE)) Loading
drivers/crypto/qat/qat_common/qat_algs.c +16 −8 Original line number Diff line number Diff line Loading @@ -73,7 +73,8 @@ ICP_QAT_HW_CIPHER_KEY_CONVERT, \ ICP_QAT_HW_CIPHER_DECRYPT) static atomic_t active_dev; static DEFINE_MUTEX(algs_lock); static unsigned int active_devs; struct qat_alg_buf { uint32_t len; Loading Loading @@ -1275,7 +1276,10 @@ static struct crypto_alg qat_algs[] = { { int qat_algs_register(void) { if (atomic_add_return(1, &active_dev) == 1) { int ret = 0; mutex_lock(&algs_lock); if (++active_devs == 1) { int i; for (i = 0; i < ARRAY_SIZE(qat_algs); i++) Loading @@ -1284,21 +1288,25 @@ int qat_algs_register(void) CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC : CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; return crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs)); ret = crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs)); } return 0; mutex_unlock(&algs_lock); return ret; } int qat_algs_unregister(void) { if (atomic_sub_return(1, &active_dev) == 0) return crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs)); return 0; int ret = 0; mutex_lock(&algs_lock); if (--active_devs == 0) ret = crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs)); mutex_unlock(&algs_lock); return ret; } int qat_algs_init(void) { atomic_set(&active_dev, 0); crypto_get_default_rng(); return 0; } Loading