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Commit 1cfea546 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Just run of the mill fixes,

  core:
   - regression fix in device unplug

  qxl:
   - regression fix for might sleep in cursor handling

  nouveau:
   - regression fix in multi-screen cursor handling

  amdgpu:
   - switch off DC by default on Kaveri and older
   - some minor fixes

  i915:
   - some GEM regression fixes
   - doublescan mode fixes

  sun4i:
   - revert fix for a regression

  sii8620 bridge:
   - misc fixes"

* tag 'drm-fixes-2018-06-22' of git://anongit.freedesktop.org/drm/drm: (28 commits)
  drm/bridge/sii8620: fix display of packed pixel modes in MHL2
  drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate
  drm/amdgpu: Refactor amdgpu_vram_mgr_bo_invisible_size helper
  drm/amdgpu: Update pin_size values before unpinning BO
  drm/amdgpu:All UVD instances share one idle_work handle
  drm/amdgpu: Don't default to DC support for Kaveri and older
  drm/amdgpu: Use kvmalloc_array for allocating VRAM manager nodes array
  drm/amd/pp: Fix uninitialized variable
  drm/i915: Enable provoking vertex fix on Gen9 systems.
  drm/i915: Fix context ban and hang accounting for client
  drm/i915: Turn off g4x DP port in .post_disable()
  drm/i915: Disallow interlaced modes on g4x DP outputs
  drm/i915: Fix PIPESTAT irq ack on i965/g4x
  drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI
  drm/i915/execlists: Avoid putting the error pointer
  drm/i915: Apply batch location restrictions before pinning
  drm/nouveau/kms/nv50-: cursors always use core channel vram ctxdma
  Revert "drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE"
  drm/atmel-hlcdc: check stride values in the first plane
  drm/bridge/sii8620: fix HDMI cable connection to dongle
  ...
parents 27db64f6 f3294568

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+9 −1
Original line number Diff line number Diff line
@@ -2158,10 +2158,18 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	switch (asic_type) {

#if defined(CONFIG_DRM_AMD_DC)

	case CHIP_BONAIRE:

	case CHIP_HAWAII:

	case CHIP_KAVERI:

	case CHIP_KABINI:

	case CHIP_MULLINS:

		/*

		 * We have systems in the wild with these ASICs that require

		 * LVDS and VGA support which is not supported with DC.

		 *

		 * Fallback to the non-DC driver here by default so as not to

		 * cause regressions.

		 */

		return amdgpu_dc > 0;

	case CHIP_HAWAII:

	case CHIP_CARRIZO:

	case CHIP_STONEY:

	case CHIP_POLARIS10:

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+10 −14
Original line number Diff line number Diff line
@@ -762,8 +762,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);

	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {

		adev->vram_pin_size += amdgpu_bo_size(bo);

		if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

			adev->invisible_pin_size += amdgpu_bo_size(bo);

		adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo);

	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {

		adev->gart_pin_size += amdgpu_bo_size(bo);

	}
@@ -790,25 +789,22 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) 
	bo->pin_count--;

	if (bo->pin_count)

		return 0;

	for (i = 0; i < bo->placement.num_placement; i++) {

		bo->placements[i].lpfn = 0;

		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;

	}

	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

	if (unlikely(r)) {

		dev_err(adev->dev, "%p validate failed for unpin\n", bo);

		goto error;

	}



	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

		adev->vram_pin_size -= amdgpu_bo_size(bo);

		if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

			adev->invisible_pin_size -= amdgpu_bo_size(bo);

		adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo);

	} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {

		adev->gart_pin_size -= amdgpu_bo_size(bo);

	}



error:

	for (i = 0; i < bo->placement.num_placement; i++) {

		bo->placements[i].lpfn = 0;

		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;

	}

	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

	if (unlikely(r))

		dev_err(adev->dev, "%p validate failed for unpin\n", bo);



	return r;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem); 
uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);

int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);



u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo);

uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);

uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+7 −7
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 
	unsigned version_major, version_minor, family_id;

	int i, j, r;



	INIT_DELAYED_WORK(&adev->uvd.inst->idle_work, amdgpu_uvd_idle_work_handler);

	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);



	switch (adev->asic_type) {

#ifdef CONFIG_DRM_AMDGPU_CIK
@@ -314,12 +314,12 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) 
	void *ptr;

	int i, j;



	cancel_delayed_work_sync(&adev->uvd.idle_work);



	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {

		if (adev->uvd.inst[j].vcpu_bo == NULL)

			continue;



		cancel_delayed_work_sync(&adev->uvd.inst[j].idle_work);



		/* only valid for physical mode */

		if (adev->asic_type < CHIP_POLARIS10) {

			for (i = 0; i < adev->uvd.max_handles; ++i)
@@ -1145,7 +1145,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 
static void amdgpu_uvd_idle_work_handler(struct work_struct *work)

{

	struct amdgpu_device *adev =

		container_of(work, struct amdgpu_device, uvd.inst->idle_work.work);

		container_of(work, struct amdgpu_device, uvd.idle_work.work);

	unsigned fences = 0, i, j;



	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
@@ -1167,7 +1167,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 
							       AMD_CG_STATE_GATE);

		}

	} else {

		schedule_delayed_work(&adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);

		schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);

	}

}
@@ -1179,7 +1179,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 
	if (amdgpu_sriov_vf(adev))

		return;



	set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst->idle_work);

	set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);

	if (set_clocks) {

		if (adev->pm.dpm_enabled) {

			amdgpu_dpm_enable_uvd(adev, true);
@@ -1196,7 +1196,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 
void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)

{

	if (!amdgpu_sriov_vf(ring->adev))

		schedule_delayed_work(&ring->adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);

		schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ struct amdgpu_uvd_inst { 
	void			*saved_bo;

	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];

	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];

	struct delayed_work	idle_work;

	struct amdgpu_ring	ring;

	struct amdgpu_ring	ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];

	struct amdgpu_irq_src	irq;
@@ -62,6 +61,7 @@ struct amdgpu_uvd { 
	bool			address_64_bit;

	bool			use_ctx_buf;

	struct amdgpu_uvd_inst		inst[AMDGPU_MAX_UVD_INSTANCES];

	struct delayed_work	idle_work;

};



int amdgpu_uvd_sw_init(struct amdgpu_device *adev);